Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen/fhdl/instance: Add instance description.

This commit is contained in:
Florent Kermarrec 2023-11-03 11:53:32 +01:00
parent 079a0a7b75
commit 18c0541e6a
1 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
litex/gen/fhdl/instance.py
View File

@ -11,7 +11,17 @@ from migen.fhdl.specials import *
# LiteX Instance Verilog Generation ---------------------------------------------------------------- # LiteX Instance Verilog Generation ----------------------------------------------------------------
def _instance_generate_verilog(instance, ns, add_data_file): def _instance_generate_verilog(instance, ns, add_data_file):
r = instance.of + " " r = ""
# Instance Description.
# ---------------------
r += "//" + "-"*78 + "\n"
r += f"// Instance {ns.get_name(instance)} of {instance.of} Module.\n"
r += "//" + "-"*78 + "\n"
# Instance Name.
# --------------
r += instance.of + " "
# Instance Parameters. # Instance Parameters.
# -------------------- # --------------------
@ -23,7 +33,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
if not first: if not first:
r += ",\n" r += ",\n"
first = False first = False
r += "\t." + p.name + "(" r += f"\t.{p.name}("
# Constant. # Constant.
if isinstance(p.value, Constant): if isinstance(p.value, Constant):
r += verilog_printexpr(ns, p.value)[0] r += verilog_printexpr(ns, p.value)[0]
@ -35,7 +45,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
r += p.value r += p.value
# String. # String.
elif isinstance(p.value, str): elif isinstance(p.value, str):
r += "\"" + p.value + "\"" r += f"\"{p.value}\""
else: else:
raise TypeError raise TypeError
r += ")" r += ")"