gen/fhdl/instance: Add instance description.
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@ -11,7 +11,17 @@ from migen.fhdl.specials import *
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# LiteX Instance Verilog Generation ----------------------------------------------------------------
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# LiteX Instance Verilog Generation ----------------------------------------------------------------
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def _instance_generate_verilog(instance, ns, add_data_file):
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def _instance_generate_verilog(instance, ns, add_data_file):
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r = instance.of + " "
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r = ""
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# Instance Description.
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# ---------------------
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r += "//" + "-"*78 + "\n"
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r += f"// Instance {ns.get_name(instance)} of {instance.of} Module.\n"
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r += "//" + "-"*78 + "\n"
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# Instance Name.
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# --------------
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r += instance.of + " "
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# Instance Parameters.
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# Instance Parameters.
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# --------------------
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# --------------------
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@ -23,7 +33,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
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if not first:
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if not first:
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r += ",\n"
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r += ",\n"
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first = False
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first = False
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r += "\t." + p.name + "("
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r += f"\t.{p.name}("
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# Constant.
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# Constant.
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if isinstance(p.value, Constant):
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if isinstance(p.value, Constant):
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r += verilog_printexpr(ns, p.value)[0]
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r += verilog_printexpr(ns, p.value)[0]
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@ -35,7 +45,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
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r += p.value
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r += p.value
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# String.
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# String.
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elif isinstance(p.value, str):
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elif isinstance(p.value, str):
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r += "\"" + p.value + "\""
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r += f"\"{p.value}\""
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else:
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else:
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raise TypeError
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raise TypeError
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r += ")"
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r += ")"
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