tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify.
This commit is contained in:
Florent Kermarrec
parent
0083e0978b
commit
18c57a64a3
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@ -1,143 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.pwm import PWM
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.cores.spi import SPIMaster, SPISlave
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from litex.build.generic_platform import *
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class Platform(GenericPlatform):
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def __init__(self, io):
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GenericPlatform.__init__(self, "extractor", io)
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def build(self, fragment, build_dir="build", **kwargs):
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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top_output = self.get_verilog(fragment)
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top_file = "top.v"
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top_output.write(top_file)
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_io = [
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("sys_clk", 0, Pins(1)),
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("sys_rst", 0, Pins(1)),
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("serial", 0,
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Subsignal("rx", Pins(1)),
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Subsignal("tx", Pins(1)),
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),
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("pwm", 0, Pins(1)),
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]
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class BaseSoC(SoCMini):
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SoCMini.mem_map["csr"] = 0x00000000
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def __init__(self, sys_clk_freq=int(100e6),
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with_pwm=False,
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with_gpio=False, gpio_width=32,
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with_spi_master=False, spi_master_data_width=8, spi_master_clk_freq=8e6,
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**kwargs):
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platform = Platform(_io)
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kwargs["integrated_rom_size"] = 0
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kwargs["integrated_sram_size"] = 0
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# CRG -------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))
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# SoCMini ---------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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if with_spi_master:
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platform.add_extension([("spi_m", 0,
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Subsignal("clk", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("mosi", Pins(1)),
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Subsignal("miso", Pins(1)),
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)])
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self.submodules.spi_m = SPIMaster(
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platform.request("spi_m"),
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spi_master_data_width,
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sys_clk_freq,
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spi_master_clk_freq,
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)
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self.add_csr("spi_m")
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if with_pwm:
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self.submodules.pwm = PWM(platform.request("pwm"))
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self.add_csr('pwm')
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if with_gpio:
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platform.add_extension([("gpio", 0, Pins(gpio_width))])
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self.submodules.gpio = GPIOTristate(platform.request("gpio"))
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self.add_csr('gpio')
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self.wb_bus = wishbone.Interface()
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self.bus.add_master(name="wb_master", master=self.wb_bus)
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self.wb_bus.connect_to_pads(self, platform, 'wb', mode='slave')
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for name, loc in sorted(self.irq.locs.items()):
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module = getattr(self, name)
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platform.add_extension([("irq_"+name, 0, Pins(1))])
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irq_pin = platform.request("irq_"+name)
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self.comb += irq_pin.eq(module.ev.irq)
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# Build -------------------------------------------------------------------------------------------
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def soc_argdict(args):
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ret = {}
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for arg in ["with_pwm", "with_uart", "with_ctrl", "with_timer",
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"with_gpio", "gpio_width",
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"with_spi_master", "spi_master_data_width", "spi_master_clk_freq",
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"csr_data_width", "csr_address_width", "csr_paging"]:
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ret[arg] = getattr(args, arg)
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return ret
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC")
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builder_args(parser)
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# Cores
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parser.add_argument("--with-pwm", action="store_true",
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help="Add PWM core")
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parser.add_argument("--with-uart", action="store_true",
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help="Add UART core")
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parser.add_argument("--with-ctrl", action="store_true",
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help="Add bus controller core")
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parser.add_argument("--with-timer", action="store_true",
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help="Add timer core")
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parser.add_argument("--with-spi-master", action="store_true",
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help="Add SPI master core")
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parser.add_argument("--spi-master-data-width", default=8, type=int,
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help="SPI master data width")
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parser.add_argument("--spi-master-clk-freq", default=8e6, type=int,
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help="SPI master output clock frequency")
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parser.add_argument("--with-gpio", action="store_true",
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help="Add GPIO core")
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parser.add_argument("--gpio-width", default=32, type=int,
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help="GPIO signals width")
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# CSR settings
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parser.add_argument("--csr-data-width", default=8, type=int,
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help="CSR bus data-width (8 or 32, default=8)")
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parser.add_argument("--csr-address-width", default=14, type=int,
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help="CSR bus address-width")
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parser.add_argument("--csr-paging", default=0x800, type=int,
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help="CSR bus paging")
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args = parser.parse_args()
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soc = BaseSoC(**soc_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,146 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Piotr Binkowski <pbinkowski@antmicro.com>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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import argparse
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from migen import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.pwm import PWM
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from litex.soc.cores.gpio import GPIOTristate
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from litex.soc.cores.spi import SPIMaster, SPISlave
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from litex.build.generic_platform import *
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# Platform -----------------------------------------------------------------------------------------
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_io = [
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("sys_clk", 0, Pins(1)),
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("sys_rst", 0, Pins(1)),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GenericPlatform):
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def __init__(self, io):
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GenericPlatform.__init__(self, "", io)
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def build(self, fragment, build_dir, **kwargs):
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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top_output = self.get_verilog(fragment)
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top_output.write("litex_core.v")
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# LiteXCore ----------------------------------------------------------------------------------------
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class LiteXCore(SoCMini):
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SoCMini.mem_map["csr"] = 0x00000000
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def __init__(self, sys_clk_freq=int(100e6),
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with_pwm = False,
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with_gpio = False, gpio_width=32,
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with_spi_master = False, spi_master_data_width=8, spi_master_clk_freq=8e6,
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**kwargs):
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platform = Platform(_io)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# SPI Master
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if with_spi_master:
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platform.add_extension([
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("spi_master", 0,
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Subsignal("clk", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("mosi", Pins(1)),
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Subsignal("miso", Pins(1)),
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)
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])
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self.submodules.spi_master = SPIMaster(
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pads = platform.request("spi_master"),
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data_width = spi_master_data_width,
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sys_clk_freq = sys_clk_freq,
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spi_clk_freq = spi_master_clk_freq,
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)
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self.add_csr("spi_master")
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# PWM
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if with_pwm:
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platform.add_extension([("pwm", 0, Pins(1))])
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self.submodules.pwm = PWM(platform.request("pwm"))
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self.add_csr("pwm")
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# GPIO
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if with_gpio:
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platform.add_extension([("gpio", 0, Pins(gpio_width))])
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self.submodules.gpio = GPIOTristate(platform.request("gpio"))
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self.add_csr("gpio")
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# Wishbone Master
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self.wb_bus = wishbone.Interface()
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self.bus.add_master(master=self.wb_bus)
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self.wb_bus.connect_to_pads(self, platform, "wb", mode="slave")
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# IRQs
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for name, loc in sorted(self.irq.locs.items()):
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module = getattr(self, name)
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platform.add_extension([("irq_"+name, 0, Pins(1))])
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irq_pin = platform.request("irq_"+name)
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self.comb += irq_pin.eq(module.ev.irq)
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# Build -------------------------------------------------------------------------------------------
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def soc_argdict(args):
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ret = {}
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for arg in [
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"with_pwm",
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"with_uart",
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"with_ctrl",
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"with_timer",
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"with_gpio",
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"gpio_width",
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"with_spi_master",
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"spi_master_data_width",
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"spi_master_clk_freq",
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"csr_data_width",
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"csr_address_width",
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"csr_paging"]:
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ret[arg] = getattr(args, arg)
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return ret
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def main():
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parser = argparse.ArgumentParser(description="LiteX standalone core generator")
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builder_args(parser)
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# Cores
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parser.add_argument("--with-pwm", action="store_true", help="Add PWM core")
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parser.add_argument("--with-uart", action="store_true", help="Add UART core")
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parser.add_argument("--with-ctrl", action="store_true", help="Add bus controller core")
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parser.add_argument("--with-timer", action="store_true", help="Add timer core")
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parser.add_argument("--with-spi-master", action="store_true", help="Add SPI master core")
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parser.add_argument("--spi-master-data-width", default=8, type=int, help="SPI master data width")
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parser.add_argument("--spi-master-clk-freq", default=8e6, type=int, help="SPI master output clock frequency")
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parser.add_argument("--with-gpio", action="store_true", help="Add GPIO core")
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parser.add_argument("--gpio-width", default=32, type=int, help="GPIO signals width")
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# CSR settings
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parser.add_argument("--csr-data-width", default=8, type=int, help="CSR bus data-width (8 or 32, default=8)")
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parser.add_argument("--csr-address-width", default=14, type=int, help="CSR bus address-width")
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parser.add_argument("--csr-paging", default=0x800, type=int, help="CSR bus paging")
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args = parser.parse_args()
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soc = LiteXCore(**soc_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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