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targets: change a7/k7ddrphy imports to s7ddrphy

This commit is contained in:
Florent Kermarrec 2018-06-12 15:39:22 +02:00
parent 3e723d152a
commit 18f86881d9
4 changed files with 8 additions and 8 deletions
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4
litex/boards/targets/arty.py
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@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.modules import MT41K128M16 from litedram.modules import MT41K128M16
from litedram.phy import a7ddrphy from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII from liteeth.phy.mii import LiteEthPHYMII
from liteeth.core.mac import LiteEthMAC from liteeth.core.mac import LiteEthMAC
@ -107,7 +107,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
# sdram # sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14) self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4") sdram_module = MT41K128M16(self.clk_freq, "1:4")

4
litex/boards/targets/kc705.py
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@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.modules import MT8JTF12864 from litedram.modules import MT8JTF12864
from litedram.phy import k7ddrphy from litedram.phy import s7ddrphy
from liteeth.phy import LiteEthPHY from liteeth.phy import LiteEthPHY
from liteeth.core.mac import LiteEthMAC from liteeth.core.mac import LiteEthMAC
@ -89,7 +89,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
# sdram # sdram
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4") sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.geom_settings,

4
litex/boards/targets/nexys4ddr.py
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@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.modules import MT47H64M16 from litedram.modules import MT47H64M16
from litedram.phy import a7ddrphy from litedram.phy import s7ddrphy
class _CRG(Module): class _CRG(Module):
@ -93,7 +93,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
# sdram # sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT47H64M16(self.clk_freq, "1:4") sdram_module = MT47H64M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.geom_settings,

4
litex/boards/targets/nexys_video.py
View File

@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.modules import MT41K256M16 from litedram.modules import MT41K256M16
from litedram.phy import a7ddrphy from litedram.phy import s7ddrphy
from liteeth.phy.s7rgmii import LiteEthPHYRGMII from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from liteeth.core.mac import LiteEthMAC from liteeth.core.mac import LiteEthMAC
@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
# sdram # sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14) self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K256M16(self.clk_freq, "1:4") sdram_module = MT41K256M16(self.clk_freq, "1:4")