replace litex.gen imports with migen imports

litex/boards/targets/arty.py

@@ -2,8 +2,8 @@
 
 import argparse
 
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.boards.platforms import arty
 

litex/boards/targets/de0nano.py

@@ -2,7 +2,8 @@
 
 import argparse
 
-from litex.gen import *
+from migen import *
+
 from litex.boards.platforms import de0nano
 
 from litex.soc.integration.soc_sdram import *

litex/boards/targets/kc705.py

@@ -2,8 +2,8 @@
 
 import argparse
 
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.boards.platforms import kc705
 

litex/boards/targets/minispartan6.py

@@ -3,8 +3,9 @@
 import argparse
 from fractions import Fraction
 
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
 from litex.boards.platforms import minispartan6
 
 from litex.soc.integration.soc_sdram import *

litex/boards/targets/nexys4ddr.py

@@ -2,8 +2,8 @@
 
 import argparse
 
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.boards.platforms import nexys4ddr
 

litex/boards/targets/nexys_video.py

@@ -2,8 +2,8 @@
 
 import argparse
 
-from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.boards.platforms import nexys_video
 

litex/boards/targets/sim.py

@@ -3,9 +3,10 @@
 import argparse
 import importlib
 
-from litex.gen import *
+from migen import *
+from migen.genlib.io import CRG
+
 from litex.boards.platforms import sim
-from litex.gen.genlib.io import CRG
 
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *

litex/boards/targets/simple.py

@@ -3,8 +3,8 @@
 import argparse
 import importlib
 
-from litex.gen import *
-from litex.gen.genlib.io import CRG
+from migen import *
+from migen.genlib.io import CRG
 
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *

litex/build/altera/common.py

@@ -1,6 +1,6 @@
-from litex.gen.fhdl.module import Module
-from litex.gen.fhdl.specials import Instance
-from litex.gen.genlib.io import DifferentialInput, DifferentialOutput
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.genlib.io import DifferentialInput, DifferentialOutput
 
 
 class AlteraDifferentialInputImpl(Module):

litex/build/altera/quartus.py

@@ -4,7 +4,7 @@
 import os
 import subprocess
 
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
 
 from litex.build.generic_platform import Pins, IOStandard, Misc
 from litex.build import tools

litex/build/generic_platform.py

@@ -1,9 +1,10 @@
 import os
 
-from litex.gen.fhdl.structure import Signal
-from litex.gen.genlib.record import Record
-from litex.gen.genlib.io import CRG
-from litex.gen.fhdl import verilog
+from migen.fhdl.structure import Signal
+from migen.genlib.record import Record
+from migen.genlib.io import CRG
+from migen.fhdl import verilog
+
 from litex.build import tools
 
 

litex/build/lattice/common.py

@@ -1,7 +1,7 @@
-from litex.gen.fhdl.module import Module
-from litex.gen.fhdl.specials import Instance
-from litex.gen.genlib.io import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.genlib.io import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
 
 
 class DiamondAsyncResetSynchronizerImpl(Module):

litex/build/lattice/diamond.py

@@ -6,8 +6,8 @@ import sys
 import subprocess
 import shutil
 
-from litex.gen.fhdl.structure import _Fragment
-from litex.gen.fhdl.verilog import DummyAttrTranslate
+from migen.fhdl.structure import _Fragment
+from migen.fhdl.verilog import DummyAttrTranslate
 
 from litex.build.generic_platform import *
 from litex.build import tools

litex/build/lattice/icestorm.py

@@ -5,7 +5,7 @@ import os
 import sys
 import subprocess
 
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
 
 from litex.build.generic_platform import *
 from litex.build import tools

litex/build/sim/platform.py

@@ -1,5 +1,6 @@
-from litex.gen.fhdl.structure import Signal
-from litex.gen.genlib.record import Record
+from migen.fhdl.structure import Signal
+from migen.genlib.record import Record
+
 from litex.build.generic_platform import GenericPlatform
 from litex.build.sim import common, verilator
 

litex/build/sim/verilator.py

@@ -5,7 +5,8 @@
 import os
 import subprocess
 
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
+
 from litex.build import tools
 from litex.build.generic_platform import *
 

litex/build/xilinx/common.py

@@ -11,12 +11,12 @@ try:
 except ImportError:
     _have_colorama = False
 
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.specials import Instance
-from litex.gen.fhdl.module import Module
-from litex.gen.genlib.cdc import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
-from litex.gen.genlib.io import *
+from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
+from migen.fhdl.module import Module
+from migen.genlib.cdc import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import *
 
 from litex.build import tools
 

litex/build/xilinx/ise.py

@@ -2,7 +2,8 @@ import os
 import subprocess
 import sys
 
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
+
 from litex.build.generic_platform import *
 from litex.build import tools
 from litex.build.xilinx import common

litex/build/xilinx/vivado.py

@@ -5,7 +5,8 @@ import os
 import subprocess
 import sys
 
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl.structure import _Fragment
+
 from litex.build.generic_platform import *
 from litex.build import tools
 from litex.build.xilinx import common

litex/gen/__init__.py

@@ -1,11 +1 @@
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.module import *
-from litex.gen.fhdl.specials import *
-from litex.gen.fhdl.bitcontainer import *
-from litex.gen.fhdl.decorators import *
-from litex.gen.fhdl.simplify import *
-
 from litex.gen.sim import *
-
-from litex.gen.genlib.record import *
-from litex.gen.genlib.fsm import *

litex/gen/fhdl/verilog.py

@@ -2,11 +2,11 @@ from functools import partial
 from operator import itemgetter
 import collections
 
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
-from litex.gen.fhdl.tools import *
-from litex.gen.fhdl.namer import build_namespace
-from litex.gen.fhdl.conv_output import ConvOutput
+from migen.fhdl.structure import *
+from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
+from migen.fhdl.tools import *
+from migen.fhdl.namer import build_namespace
+from migen.fhdl.conv_output import ConvOutput
 
 
 _reserved_keywords = {

litex/gen/sim/__init__.py

@@ -1 +1 @@
-from litex.gen.sim.core import Simulator, run_simulation, passive
+from migen.sim.core import Simulator, run_simulation, passive

litex/gen/sim/core.py

@@ -3,18 +3,18 @@ import collections
 import inspect
 from functools import wraps
 
-from litex.gen.fhdl.structure import *
-from litex.gen.fhdl.structure import (_Value, _Statement,
+from migen.fhdl.structure import *
+from migen.fhdl.structure import (_Value, _Statement,
                                   _Operator, _Slice, _ArrayProxy,
                                   _Assign, _Fragment)
-from litex.gen.fhdl.bitcontainer import value_bits_sign
-from litex.gen.fhdl.tools import (list_targets, list_signals,
+from migen.fhdl.bitcontainer import value_bits_sign
+from migen.fhdl.tools import (list_targets, list_signals,
                               insert_resets, lower_specials)
-from litex.gen.fhdl.simplify import MemoryToArray
-from litex.gen.fhdl.specials import _MemoryLocation
-from litex.gen.fhdl.module import Module
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
-from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter
+from migen.fhdl.simplify import MemoryToArray
+from migen.fhdl.specials import _MemoryLocation
+from migen.fhdl.module import Module
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.sim.vcd import VCDWriter, DummyVCDWriter
 
 
 class ClockState:

litex/gen/sim/vcd.py

@@ -4,7 +4,7 @@ import os
 from collections import OrderedDict
 import shutil
 
-from litex.gen.fhdl.namer import build_namespace
+from migen.fhdl.namer import build_namespace
 
 
 def vcd_codes():

litex/soc/cores/code_8b10b.py

@@ -12,7 +12,7 @@ Note: This encoding is *not* used by DVI/HDMI (that uses a *different* 8b/10b
 scheme called TMDS).
 """
 
-from litex.gen import *
+from migen import *
 
 
 def disparity(word, nbits):

litex/soc/cores/cordic.py

@@ -17,7 +17,7 @@
 
 from math import atan, atanh, log, sqrt, pi
 
-from litex.gen import *
+from migen import *
 
 
 class TwoQuadrantCordic(Module):

litex/soc/cores/cpu/lm32/core.py

@@ -1,6 +1,6 @@
 import os
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/cpu/mor1kx/core.py

@@ -1,6 +1,6 @@
 import os
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/cpu/picorv32/core.py

@@ -1,6 +1,6 @@
 import os
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/dna.py

@@ -1,6 +1,7 @@
 # Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
 
-from litex.gen import *
+from migen import *
+
 from litex.soc.interconnect.csr import *
 
 

litex/soc/cores/frequency_meter.py

@@ -1,6 +1,6 @@
-from litex.gen import *
-from litex.gen.genlib.cdc import MultiReg, GrayCounter
-from litex.gen.genlib.cdc import GrayDecoder
+from migen import *
+from migen.genlib.cdc import MultiReg, GrayCounter
+from migen.genlib.cdc import GrayDecoder
 
 from litex.soc.interconnect.csr import *
 

litex/soc/cores/gpio.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.cdc import MultiReg
+from migen import *
+from migen.genlib.cdc import MultiReg
 
 from litex.soc.interconnect.csr import *
 

litex/soc/cores/identifier.py

@@ -1,4 +1,4 @@
-from litex.gen import *
+from migen import *
 
 
 class Identifier(Module):

litex/soc/cores/nor_flash_16.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.fsm import FSM, NextState
+from migen import *
+from migen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import wishbone
 

litex/soc/cores/spi.py

@@ -1,6 +1,7 @@
 from itertools import product
 
-from litex.gen import *
+from migen import *
+
 from litex.soc.interconnect.csr import *
 
 

litex/soc/cores/spi_flash.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.misc import timeline
+from migen import *
+from migen.genlib.misc import timeline
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus

litex/soc/cores/timer.py

@@ -1,4 +1,4 @@
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *

litex/soc/cores/uart.py

@@ -1,6 +1,6 @@
-from litex.gen import *
-from litex.gen.genlib.record import Record
-from litex.gen.genlib.cdc import MultiReg
+from migen import *
+from migen.genlib.record import Record
+from migen.genlib.cdc import MultiReg
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *

litex/soc/cores/xadc.py

@@ -1,6 +1,7 @@
 # Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
 
-from litex.gen import *
+from migen import *
+
 from litex.soc.interconnect.csr import *
 
 

litex/soc/integration/cpu_interface.py

@@ -1,6 +1,6 @@
 import os
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.interconnect.csr import CSRStatus
 

litex/soc/integration/sdram_init.py

@@ -1,4 +1,4 @@
-from litex.gen import log2_int
+from migen import log2_int
 
 
 def get_sdram_phy_header(sdram_phy_settings):

litex/soc/integration/soc_core.py

@@ -1,6 +1,6 @@
 from operator import itemgetter
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.cores import identifier, timer, uart
 from litex.soc.cores.cpu import lm32, mor1kx, picorv32

litex/soc/integration/soc_sdram.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.record import *
+from migen import *
+from migen.genlib.record import *
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import AutoCSR
@@ -79,7 +79,7 @@ class SoCSDRAM(SoCCore):
             # Remove this workaround when fixed by Xilinx.
             from litex.build.xilinx.vivado import XilinxVivadoToolchain
             if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
-                from litex.gen.fhdl.simplify import FullMemoryWE
+                from migen.fhdl.simplify import FullMemoryWE
                 self.submodules.l2_cache = FullMemoryWE()(l2_cache)
             else:
                 self.submodules.l2_cache = l2_cache

litex/soc/interconnect/axi.py

@@ -6,8 +6,9 @@
 
 import math
 
-from litex.gen import *
-from litex.gen.genlib.record import *
+from migen import *
+from migen.genlib.record import *
+
 from litex.soc.interconnect import csr_bus
 
 # Layout of AXI4 Lite Bus
@@ -179,7 +180,7 @@ class AXILite2CSR(Module):
         )
 
 
-from litex.gen.sim import run_simulation
+from migen.sim import run_simulation
 from litex.soc.interconnect import csr, csr_bus
 
 def test_axilite2csr():

litex/soc/interconnect/csr.py

@@ -24,9 +24,9 @@ class, which provides ``get_csrs`` and ``get_memories`` methods that scan for
 CSR and memory attributes and return their list.
 """
 
-from litex.gen import *
-from litex.gen.util.misc import xdir
-from litex.gen.fhdl.tracer import get_obj_var_name
+from migen import *
+from migen.util.misc import xdir
+from migen.fhdl.tracer import get_obj_var_name
 
 
 class _CSRBase(DUID):

litex/soc/interconnect/csr_bus.py

@@ -6,10 +6,10 @@ The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing
 the configuration and status registers of cores from software.
 """
 
-from litex.gen import *
-from litex.gen.genlib.record import *
-from litex.gen.genlib.misc import chooser
-from litex.gen.util.misc import xdir
+from migen import *
+from migen.genlib.record import *
+from migen.genlib.misc import chooser
+from migen.util.misc import xdir
 
 from litex.soc.interconnect import csr
 from litex.soc.interconnect.csr import CSRStorage

litex/soc/interconnect/csr_eventmanager.py

@@ -6,8 +6,8 @@ controllers.
 from functools import reduce
 from operator import or_
 
-from litex.gen import *
-from litex.gen.util.misc import xdir
+from migen import *
+from migen.util.misc import xdir
 
 from litex.soc.interconnect.csr import *
 

litex/soc/interconnect/stream.py

@@ -1,16 +1,16 @@
-from litex.gen import *
-from litex.gen.genlib.record import *
-from litex.gen.genlib import fifo
+from migen import *
+from migen.genlib.record import *
+from migen.genlib import fifo
 
 (DIR_SINK, DIR_SOURCE) = range(2)
 
-def _make_m2s(layout, reset_less=False):
+def _make_m2s(layout):
     r = []
     for f in layout:
         if isinstance(f[1], (int, tuple)):
-            r.append((f[0], f[1], DIR_M_TO_S, reset_less))
+            r.append((f[0], f[1], DIR_M_TO_S))
         else:
-            r.append((f[0], _make_m2s(f[1], reset_less)))
+            r.append((f[0], _make_m2s(f[1])))
     return r
 
 
@@ -34,8 +34,8 @@ class EndpointDescription:
             ("ready", 1, DIR_S_TO_M),
             ("first", 1, DIR_M_TO_S),
             ("last", 1, DIR_M_TO_S),
-            ("payload", _make_m2s(self.payload_layout, True)),
-            ("param", _make_m2s(self.param_layout, True))
+            ("payload", _make_m2s(self.payload_layout)),
+            ("param", _make_m2s(self.param_layout))
         ]
         return full_layout
 
@@ -359,7 +359,7 @@ class StrideConverter(Module):
 # XXX
 
 from copy import copy
-from litex.gen.util.misc import xdir
+from migen.util.misc import xdir
 
 def _rawbits_layout(l):
     if isinstance(l, int):

litex/soc/interconnect/stream_packet.py

@@ -1,7 +1,7 @@
-from litex.gen import *
-from litex.gen.genlib.roundrobin import *
-from litex.gen.genlib.record import *
-from litex.gen.genlib.fsm import FSM, NextState
+from migen import *
+from migen.genlib.roundrobin import *
+from migen.genlib.record import *
+from migen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import stream
 

litex/soc/interconnect/stream_sim.py

@@ -2,7 +2,8 @@ import random
 import math
 from copy import deepcopy
 
-from litex.gen import *
+from migen import *
+
 from litex.soc.interconnect import stream
 
 # TODO: clean up code below

litex/soc/interconnect/wishbone.py

@@ -1,11 +1,11 @@
 from functools import reduce
 from operator import or_
 
-from litex.gen import *
-from litex.gen.genlib import roundrobin
-from litex.gen.genlib.record import *
-from litex.gen.genlib.misc import split, displacer, chooser
-from litex.gen.genlib.fsm import FSM, NextState
+from migen import *
+from migen.genlib import roundrobin
+from migen.genlib.record import *
+from migen.genlib.misc import split, displacer, chooser
+from migen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import csr
 

litex/soc/interconnect/wishbone2csr.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.misc import timeline
+from migen import *
+from migen.genlib.misc import timeline
 
 from litex.soc.interconnect import csr_bus, wishbone
 

litex/soc/interconnect/wishbonebridge.py

@@ -1,8 +1,8 @@
-from litex.gen import *
+from migen import *
 
-from litex.gen.genlib.misc import chooser, WaitTimer
-from litex.gen.genlib.record import Record
-from litex.gen.genlib.fsm import FSM, NextState
+from migen.genlib.misc import chooser, WaitTimer
+from migen.genlib.record import Record
+from migen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect import stream

test/test_bitslip.py

@@ -1,8 +1,8 @@
 import unittest
 import random
 
-from litex.gen import *
-from litex.gen.genlib.misc import BitSlip
+from migen import *
+from migen.genlib.misc import BitSlip
 
 
 class BitSlipModel:

test/test_code_8b10b.py

@@ -2,7 +2,7 @@ import unittest
 import random
 from collections import namedtuple
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.cores import code_8b10b
 

test/test_gearbox.py

@@ -1,8 +1,8 @@
 import unittest
 import random
 
-from litex.gen import *
-from litex.gen.genlib.cdc import Gearbox
+from migen import *
+from migen.genlib.cdc import Gearbox
 
 # TODO:
 # connect two gearbox together:

test/test_targets.py

@@ -1,7 +1,7 @@
 import unittest
 import os
 
-from litex.gen import *
+from migen import *
 
 from litex.soc.integration.builder import *