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integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. 

This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.
This commit is contained in:
Florent Kermarrec 2020-07-29 11:10:05 +02:00
parent 6576416b8e
commit 1938ce363d
1 changed files with 7 additions and 0 deletions
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7
litex/soc/integration/soc.py
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@ -1157,6 +1157,13 @@ class LiteXSoC(SoC):
# Add SDRAM region # Add SDRAM region
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
# Add CPU's direct memory buses (if not already declared) ----------------------------------
if hasattr(self.cpu, "add_memory_buses"):
self.cpu.add_memory_buses(
address_width = 32,
data_width = self.sdram.crossbar.controller.data_width
)
# SoC [<--> L2 Cache] <--> LiteDRAM -------------------------------------------------------- # SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
if len(self.cpu.memory_buses): if len(self.cpu.memory_buses):
# When CPU has at least a direct memory bus, connect them directly to LiteDRAM. # When CPU has at least a direct memory bus, connect them directly to LiteDRAM.