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litex_server: update pcie and remove bar_size parameter

This commit is contained in:
Florent Kermarrec 2018-09-05 13:01:51 +02:00
parent c5a2d6f3ec
commit 1944289e64
2 changed files with 7 additions and 9 deletions
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9
litex/soc/tools/remote/comm_pcie.py
View File

@ -2,9 +2,8 @@ import mmap
class CommPCIe: class CommPCIe:
def __init__(self, bar, bar_size, debug=False): def __init__(self, bar, debug=False):
self.bar = bar self.bar = bar
self.bar_size = bar_size
self.debug = debug self.debug = debug
def open(self): def open(self):
@ -12,7 +11,7 @@ class CommPCIe:
return return
self.sysfs = open(self.bar, "r+b") self.sysfs = open(self.bar, "r+b")
self.sysfs.flush() self.sysfs.flush()
self.mmap = mmap.mmap(self.sysfs.fileno(), self.bar_size) self.mmap = mmap.mmap(self.sysfs.fileno(), 0)
def close(self): def close(self):
if not hasattr(self, "sysfs"): if not hasattr(self, "sysfs"):
@ -27,7 +26,7 @@ class CommPCIe:
length_int = 1 if length is None else length length_int = 1 if length is None else length
for i in range(length_int): for i in range(length_int):
self.mmap.seek(addr + 4*i) self.mmap.seek(addr + 4*i)
value = int.from_bytes(self.mmap.read(4), "big") value = int.from_bytes(self.mmap.read(4), byteorder="little")
if self.debug: if self.debug:
print("read {:08x} @ {:08x}".format(value, addr + 4*i)) print("read {:08x} @ {:08x}".format(value, addr + 4*i))
if length is None: if length is None:
@ -39,6 +38,6 @@ class CommPCIe:
data = data if isinstance(data, list) else [data] data = data if isinstance(data, list) else [data]
length = len(data) length = len(data)
for i, value in enumerate(data): for i, value in enumerate(data):
self.mmap[addr + 4*i:addr + 4*(i + 1)] = value.to_bytes(4, byteorder="big") self.mmap[addr + 4*i:addr + 4*(i + 1)] = value.to_bytes(4, byteorder="little")
if self.debug: if self.debug:
print("write {:08x} @ {:08x}".format(value, addr + 4*i)) print("write {:08x} @ {:08x}".format(value, addr + 4*i))

7
litex/soc/tools/remote/litex_server.py
View File

@ -97,7 +97,7 @@ def main():
print("usages:") print("usages:")
print("litex_server uart [port] [baudrate]") print("litex_server uart [port] [baudrate]")
print("litex_server udp [server] [server_port]") print("litex_server udp [server] [server_port]")
print("litex_server pcie [bar] [bar_size]") print("litex_server pcie [bar]")
sys.exit() sys.exit()
comm = sys.argv[1] comm = sys.argv[1]
if comm == "uart": if comm == "uart":
@ -123,13 +123,12 @@ def main():
elif comm == "pcie": elif comm == "pcie":
from litex.soc.tools.remote import CommPCIe from litex.soc.tools.remote import CommPCIe
bar = "" bar = ""
bar_size = 1024*1024
if len(sys.argv) > 2: if len(sys.argv) > 2:
bar = sys.argv[2] bar = sys.argv[2]
if len(sys.argv) > 3: if len(sys.argv) > 3:
bar_size = int(sys.argv[3]) bar_size = int(sys.argv[3])
print("[CommPCIe] bar: {} / bar_size: {} / ".format(bar, bar_size), end="") print("[CommPCIe] bar: {} / ".format(bar), end="")
comm = CommPCIe(bar, bar_size) comm = CommPCIe(bar)
else: else:
raise NotImplementedError raise NotImplementedError