litex_server: update pcie and remove bar_size parameter
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parent
c5a2d6f3ec
commit
1944289e64
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@ -2,9 +2,8 @@ import mmap
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class CommPCIe:
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def __init__(self, bar, bar_size, debug=False):
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def __init__(self, bar, debug=False):
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self.bar = bar
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self.bar_size = bar_size
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self.debug = debug
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def open(self):
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@ -12,7 +11,7 @@ class CommPCIe:
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return
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self.sysfs = open(self.bar, "r+b")
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self.sysfs.flush()
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self.mmap = mmap.mmap(self.sysfs.fileno(), self.bar_size)
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self.mmap = mmap.mmap(self.sysfs.fileno(), 0)
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def close(self):
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if not hasattr(self, "sysfs"):
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@ -27,7 +26,7 @@ class CommPCIe:
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length_int = 1 if length is None else length
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for i in range(length_int):
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self.mmap.seek(addr + 4*i)
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value = int.from_bytes(self.mmap.read(4), "big")
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value = int.from_bytes(self.mmap.read(4), byteorder="little")
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if self.debug:
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print("read {:08x} @ {:08x}".format(value, addr + 4*i))
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if length is None:
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@ -39,6 +38,6 @@ class CommPCIe:
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data = data if isinstance(data, list) else [data]
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length = len(data)
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for i, value in enumerate(data):
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self.mmap[addr + 4*i:addr + 4*(i + 1)] = value.to_bytes(4, byteorder="big")
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self.mmap[addr + 4*i:addr + 4*(i + 1)] = value.to_bytes(4, byteorder="little")
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if self.debug:
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print("write {:08x} @ {:08x}".format(value, addr + 4*i))
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@ -97,7 +97,7 @@ def main():
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print("usages:")
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print("litex_server uart [port] [baudrate]")
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print("litex_server udp [server] [server_port]")
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print("litex_server pcie [bar] [bar_size]")
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print("litex_server pcie [bar]")
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sys.exit()
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comm = sys.argv[1]
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if comm == "uart":
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@ -123,13 +123,12 @@ def main():
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elif comm == "pcie":
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from litex.soc.tools.remote import CommPCIe
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bar = ""
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bar_size = 1024*1024
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if len(sys.argv) > 2:
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bar = sys.argv[2]
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if len(sys.argv) > 3:
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bar_size = int(sys.argv[3])
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print("[CommPCIe] bar: {} / bar_size: {} / ".format(bar, bar_size), end="")
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comm = CommPCIe(bar, bar_size)
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print("[CommPCIe] bar: {} / ".format(bar), end="")
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comm = CommPCIe(bar)
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else:
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raise NotImplementedError
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