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cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus

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Thomas Watson 2022-08-05 02:20:03 +00:00
parent 926fb9a30a
commit 195cc915ed
1 changed files with 4 additions and 0 deletions
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4
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -369,6 +369,10 @@ class VexRiscvSMP(CPU):
from litex.build.altera import AlteraPlatform from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform): if isinstance(platform, AlteraPlatform):
ram_filename = "Ram_1w_1rs_Intel.v" ram_filename = "Ram_1w_1rs_Intel.v"
# define SYNTHESIS verilog name to avoid issues with unsupported
# functions
platform.toolchain.additional_qsf_commands.append(
'set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"')
# On Efinix platforms, use specific implementation. # On Efinix platforms, use specific implementation.
from litex.build.efinix import EfinixPlatform from litex.build.efinix import EfinixPlatform
if isinstance(platform, EfinixPlatform): if isinstance(platform, EfinixPlatform):