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interconnect/wishbone: Add linear burst support to DownConverter

This commit is contained in:
Marcus Comstedt 2023-10-07 09:25:08 +02:00
parent 5380df3994
commit 196b68e4af
1 changed files with 14 additions and 1 deletions
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15
litex/soc/interconnect/wishbone.py
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@ -285,8 +285,21 @@ class DownConverter(Module):
# Control Path. # Control Path.
self.comb += [ self.comb += [
done.eq(count == (ratio - 1)), done.eq(count == (ratio - 1)),
Case(master.cti, {
# incrementing address burst cycle
CTI_BURST_INCREMENTING: slave.cti.eq(CTI_BURST_INCREMENTING),
# end current burst cycle
CTI_BURST_END: slave.cti.eq(Mux(done, CTI_BURST_END,
CTI_BURST_INCREMENTING)),
# unsupported burst cycle
"default": slave.cti.eq(CTI_BURST_NONE),
}),
# wrap conversion not supported
If(master.bte != 0, slave.cti.eq(CTI_BURST_NONE)),
If(master.stb & master.cyc, If(master.stb & master.cyc,
skip.eq(slave.sel == 0), skip.eq((slave.sel == 0) & (slave.cti == CTI_BURST_NONE)),
slave.cyc.eq(~skip), slave.cyc.eq(~skip),
slave.stb.eq(~skip), slave.stb.eq(~skip),
slave.we.eq(master.we), slave.we.eq(master.we),