etherbone: fix addressing

liteeth/core/etherbone/record.py

@@ -52,7 +52,7 @@ class LiteEthEtherboneRecordReceiver(Module):
 			source.eop.eq(counter.value == fifo.source.wcount-1),
 			source.count.eq(fifo.source.wcount),
 			source.be.eq(fifo.source.byte_enable),
-			source.addr.eq(base_addr.q + counter.value),
+			source.addr.eq(base_addr.q[2:] + counter.value),
 			source.we.eq(1),
 			source.data.eq(fifo.source.data),
 			fifo.source.ack.eq(source.ack),
@@ -80,7 +80,7 @@ class LiteEthEtherboneRecordReceiver(Module):
 			source.eop.eq(counter.value == fifo.source.rcount-1),
 			source.count.eq(fifo.source.rcount),
 			source.base_addr.eq(base_addr.q),
-			source.addr.eq(fifo.source.data),
+			source.addr.eq(fifo.source.data[2:]),
 			fifo.source.ack.eq(source.ack),
 			If(source.stb & source.ack,
 				counter.ce.eq(1),

liteeth/test/etherbone_tb.py

@@ -86,7 +86,7 @@ class TB(Module):
 
 			# test reads
 			if test_reads:
-				reads_addrs = [j for j in range(16)]
+				reads_addrs = [0x1000 + 4*j for j in range(16)]
 				reads = etherbone.EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
 				record = etherbone.EtherboneRecord()
 				record.writes = None

test/test_etherbone.py

@@ -1,7 +1,7 @@
 import socket, time
 from liteeth.test.model.etherbone import *
 
-SRAM_BASE = 0x02000000//4
+SRAM_BASE = 0x02000000
 
 import socket
 sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
@@ -36,7 +36,7 @@ sock.sendto(bytes(packet), ("192.168.1.40", 20000))
 time.sleep(0.01)
 
 # test reads
-reads_addrs = [SRAM_BASE+j for j in range(16)]
+reads_addrs = [SRAM_BASE+4*j for j in range(16)]
 reads = EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
 record = EtherboneRecord()
 record.writes = None