mac: fix missing core csr generation

2015-02-16 14:44:36 +01:00 · 2015-02-16 14:44:36 +01:00 · 67958f7448
parent aedc964908
commit 67958f7448
1 changed files with 1 additions and 1 deletions
--- a/liteeth/mac/init.py
+++ b/liteeth/mac/init.py
@ -23,7 +23,7 @@ class LiteEthMAC(Module, AutoCSR):
 			self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
 			self.comb += Port.connect(self.interface, self.core)
 			self.ev, self.bus = self.interface.sram.ev, self.interface.bus
-			self.csrs = self.interface.get_csrs()
+			self.csrs = self.interface.get_csrs() + self.core.get_csrs()
 		elif interface == "dma":
 			raise NotImplementedError
 		else: