soc/add_etherbone: Revert sys_clk domain renaming when ethmac is disabled.

2024-02-09 15:10:47 +01:00 · 2024-02-09 15:10:47 +01:00 · 1b32d8a341
parent afcf78f643
commit 1b32d8a341
1 changed files with 3 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1844,7 +1844,9 @@ class LiteXSoC(SoC):
            # Use PHY's eth_tx/eth_rx clock domains.
            ethcore = ClockDomainsRenamer({
                "eth_tx": phy_cd + "_tx",
-                "eth_rx": phy_cd + "_rx"})(ethcore)
+                "eth_rx": phy_cd + "_rx",
+                "sys"   : {True: "sys", False: phy_cd + "_rx"}[with_ethmac],
+            })(ethcore)
        self.add_module(name=f"ethcore_{name}", module=ethcore)

        etherbone_cd = "sys"