bus/dfi: fix multiphase naming

2012-02-19 17:57:04 +01:00 · 2012-02-19 17:57:04 +01:00 · 1b8cb5b46c
parent d8d4e81b6e
commit 1b8cb5b46c
1 changed files with 2 additions and 2 deletions
--- a/migen/bus/dfi.py
+++ b/migen/bus/dfi.py
@ -34,9 +34,9 @@ class Interface:
 				if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
 					if add_suffix:
 						if signal[0] == M_TO_S:
-							suffix = "_p" + int(n)
+							suffix = "_p" + str(n)
 						else:
-							suffix = "_w" + int(n)
+							suffix = "_w" + str(n)
 					else:
 						suffix = ""
 					r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))