CHANGES: Update.
This commit is contained in:
Florent Kermarrec
parent
c0d3775dcd
commit
1c4d64f46b
95
CHANGES
95
CHANGES
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@ -6,46 +6,77 @@
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- cpu/vexriscv: Fix compilation with new binutils.
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- cpu/vexriscv: Fix compilation with new binutils.
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- soc/LiteXSocArgumentParser: Fix --cpu-type parsing.
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- soc/LiteXSocArgumentParser: Fix --cpu-type parsing.
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- litex_sim: Fix --with-ethernet.
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- litex_sim: Fix --with-ethernet.
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- liblitesdcard: Fix SDCard initialization corner cases.
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- liblitedram: Enable sdram_init/mr_write for SDRAM.
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- export/get_memory_x: Replace SPIFlash with ROM.
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- soc/cores/video: Fix operation with some monitors (set data to 0 during blanking).
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- tools/remote/comm_usb: Fix multi-word reads/writes.
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- build/lattice/oxide: Fix ES posfix on device name.
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- interconnect/axi: Fix AXIArbiter corner case.
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- litex_server/client: Fix remapping over CommPCIe.
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- LitePCIe: Fix LiteUART support with multi-boards.
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[> Added Features
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[> Added Features
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-----------------
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-----------------
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- litex_setup: Add -tag support for install/update.
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- litex_setup: Add -tag support for install/update.
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- tools: Add initial LiteX standalone SoC generator.
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- tools: Add initial LiteX standalone SoC generator.
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- cores/ram: Add Xilinx's FIFO_SYNC_MACRO equivalent.
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- cores/ram: Add Xilinx's FIFO_SYNC_MACRO equivalent.
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- LitePCIe: Always use 24-bit depth fields on LitePCIeBuffering to simplify software.
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- LitePCIe: Always use 24-bit depth fields on LitePCIeBuffering to simplify software.
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- gen/fhdl: Integrate Migen namer to give us more flexibility.
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- gen/fhdl: Integrate Migen namer to give us more flexibility.
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- fhdl/memory: Prefix memory files with build name to simplify reuse/integration.
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- fhdl/memory: Prefix memory files with build name to simplify reuse/integration.
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- cpu/rocket: Add more variants.
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- cpu/rocket: Add more variants.
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- cores/video: Enable driving both + and - diff outs to compensate hardware issues.
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- cores/video: Enable driving both + and - diff outs to compensate hardware issues.
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- build: Add intial OSFPGA Foedag/Raptor build backend.
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- build: Add intial OSFPGA Foedag/Raptor build backend.
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- cpu/cva5: Add initial CVA5 CPU support (ex Taiga).
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- cpu/cva5: Add initial CVA5 CPU support (ex Taiga).
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- LiteSATA: Add IRQ and Identify support.
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- LiteSATA: Add IRQ and Identify support.
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- clock/intel: Improve to find the best PLL config.
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- clock/intel: Improve to find the best PLL config.
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- cpu/cva6: Add initial CVA6 CPU support (ex Ariane).
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- cpu/cva6: Add initial CVA6 CPU support (ex Ariane).
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- bios: Improve config flags.
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- bios: Improve config flags.
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- tools: Add I2s/MMCM support to litex_json2dts_zephyr.
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- tools: Add I2s/MMCM support to litex_json2dts_zephyr.
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- clock/gowin: Add GW2A support.
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- clock/gowin: Add GW2A support.
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- bios: Disable LTO (does not work in all cases, needs to be investigated).
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- bios: Disable LTO (does not work in all cases, needs to be investigated).
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- CI: Test more RISC-V CPUs and OpenRisc CPUs in CI.
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- CI: Test more RISC-V CPUs and OpenRisc CPUs in CI.
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- bios: Add CONFIG_NO_BOOT to allow disabling boot sequence.
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- bios: Add CONFIG_NO_BOOT to allow disabling boot sequence.
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- export: Allow disabling CSR_BASE define in csr.h.
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- export: Allow disabling CSR_BASE define in csr.h.
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- build/openocd: Update for compatibility with upstream OpenOCD.
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- build/openocd: Update for compatibility with upstream OpenOCD.
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- cpu/openc906: Add initial OpenC906 support (open version of the Allwinner's D1 chip).
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- cpu/openc906: Add initial OpenC906 support (open version of the Allwinner's D1 chip).
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- soc: Add automatic bridging between AXI <-> AXI-Lite <-> Wishbone.
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- soc: Add automatic bridging between AXI <-> AXI-Lite <-> Wishbone.
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- soc: Add AXI-Full bus support.
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- soc: Add AXI-Full bus support.
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- interconnect: Add AXI DownConverted and Interconnect/Crossbar.
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- interconnect: Add AXI DownConverted and Interconnect/Crossbar.
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- interconnect: Create axi directory and split code.
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- interconnect: Create axi directory and split code.
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- soc: Modify SoC finalization order for more flexibility.
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- soc: Modify SoC finalization order for more flexibility.
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- soc: Add --bus-interconnect parameter to select interconect: shared/crossbar.
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- soc: Add --bus-interconnect parameter to select interconect: shared/crossbar.
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- valentyusb: Package and install it with LiteX.
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- valentyusb: Package and install it with LiteX.
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- bios/mem_list: Align Mem Regions.
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- bios/mem_list: Align Mem Regions.
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- build: Introduce GenericToolchain to cleanup/simplify build backends.
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- soc/etherbone: Expose broadcast capability.
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- build/lattice: Add MCLK frequency support.
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- cpu/cva6: Add IRQ support.
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- cores/clock: Add manual placement support to ECP5PLL.
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- cores/leds: Add polarity support.
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- cpu/neorv32: Switch to new NeoRV32 LiteX Core Complex and add variants support.
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- cores/gpio: Add optional reset value.
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- litex_client: Add --host support for remote operation.
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- sim/verilator: Add jobs number support (to limit RAM usage with large SoCs/CPUs).
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- soc/SocBusHandler Add get_address_width method to simplify peripheral integration.
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- bios: Expose BIOS console parameters (to enable/disable history/autocomplete).
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- bios: Expose BIOS LTO configuration.
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- litex_json2renode: Update.
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- build: Introduce YosysNextPNRToolchain to cleanup/simplify Yosys support.
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- bios: Add buttons support/command.
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- litex_client: Add XADC/Identifier/Leds/Buttons support to GUI.
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- cpu/NaxRiscv: Update.
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- build/generic_platofrm: Add add_connector methode to allow extending connectors.
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- litex_server/client: Add initial information exchange between server/client.
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- LitePCIe: Improve 64-bit support.
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[> API changes/Deprecation
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[> API changes/Deprecation
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--------------------------
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--------------------------
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- LiteX-Boards : Remove short import support on platforms/targets.
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- LiteX-Boards : Remove short import support on platforms/targets.
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- tools: Rename litex_gen to litex_periph_gen.
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- tools: Rename litex_gen to litex_periph_gen.
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- LiteX-Boards: Only generate SoC/Software headers when --build is set
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- LiteX-Boards: Only generate SoC/Software headers when --build is set
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- Symbiflow: Rename to F4PGA.
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- Symbiflow: Rename to F4PGA.
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- mkmsscimg: Rename to crcfbigen.
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[> 2022.04, released on May 3th 2022
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[> 2022.04, released on May 3th 2022
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------------------------------------
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------------------------------------
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