clock/lattice_ecp5: Fix and rework 4-output solver implementation.
The implementation was causing regressions on actual designs, rework done: - Only keep a common iteration loop as before. - Add iteration on CLKO dividers (to fall in the VCO range). - Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it. - If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
This commit is contained in:
Florent Kermarrec
parent
751e99690e
commit
1ce48a973b
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@ -1,7 +1,7 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 George Hilliard <thirtythreeforty@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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@ -63,69 +63,51 @@ class ECP5PLL(Module):
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def compute_config(self):
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config = {}
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def in_range(n, r):
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(r_min, r_max) = r
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return n >= r_min and n <= r_max
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def found_clk(n, f, d, p):
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config["clko{}_freq".format(n)] = f
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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# Iterate on CLKI dividers...
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for clki_div in range(*self.clki_div_range):
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if not in_range(self.clkin_freq / clki_div, self.pfd_freq_range):
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# Check if in PFD range.
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(pfd_freq_min, pfd_freq_max) = self.pfd_freq_range
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if not (pfd_freq_min <= self.clkin_freq/clki_div <= pfd_freq_max):
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continue
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config["clki_div"] = clki_div
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# Iterate on CLKO dividers... (to get us in VCO range)
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for clkofb_div in range(*self.clko_div_range):
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# Iterate on CLKFB dividers...
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for clkfb_div in range(*self.clkfb_div_range):
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# pick a suitable feedback clock
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found_fb = None
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for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
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if dpa and self.dpa_en:
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# cannot use clocks whose phase the user will change
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continue
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for d in range(*self.clko_div_range):
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vco_freq = self.clkin_freq/clki_div*clkfb_div*d
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clk_freq = vco_freq/d
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if in_range(vco_freq, self.vco_freq_range) \
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and abs(clk_freq - f) <= f*m:
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found_fb = n
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found_clk(n, f, d, p)
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break
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if found_fb is not None:
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break
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else:
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# none found, try to use a new output
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for d in range(*self.clko_div_range):
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vco_freq = self.clkin_freq/clki_div*clkfb_div*d
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clk_freq = vco_freq/d
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if self.nclkouts < self.nclkouts_max \
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and in_range(vco_freq, self.vco_freq_range) \
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and in_range(clk_freq, self.clko_freq_range):
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found_fb = self.nclkouts
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found_clk(found_fb, clk_freq, d, 0)
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break
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else:
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continue
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# vco_freq is known, compute remaining clocks' output settings
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vco_freq = (self.clkin_freq/clki_div)*clkfb_div*clkofb_div
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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all_valid = True
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# If in VCO range, find dividers for all outputs.
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if vco_freq_min <= vco_freq <= vco_freq_max:
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config["clkfb"] = None
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for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
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if n == found_fb:
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continue # already picked this one
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valid = False
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for d in range(*self.clko_div_range):
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clk_freq = vco_freq/d
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# If output is valid, save config.
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if abs(clk_freq - f) <= f*m:
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found_clk(n, f, d, p)
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config["clko{}_freq".format(n)] = clk_freq
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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valid = True
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# Check if ouptut can be used as feedback, if so use it.
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# (We cannot use clocks with dynamic phase adjustment enabled)
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if (d == clkofb_div) and (not (dpa and self.dpa_en)):
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config["clkfb"] = n
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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if found_fb > self.nclkouts:
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self.create_clkout(ClockDomain('feedback'), vco_freq / clkfb_div)
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# If no output suitable for feedback, create a new output for it.
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if config["clkfb"] is None:
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# We need at least a free output...
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assert self.nclkouts < self.nclkouts_max
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config["clkfb"] = self.nclkouts
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self.clkouts[self.nclkouts] = (Signal(), 0, 0, 0, 0)
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config[f"clko{self.nclkouts}_div"] = int((vco_freq*clki_div)/(self.clkin_freq*clkfb_div))
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config["vco"] = vco_freq
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config["clkfb"] = found_fb
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config["clkfb_div"] = clkfb_div
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compute_config_log(self.logger, config)
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return config
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@ -164,17 +146,17 @@ class ECP5PLL(Module):
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i_CLKI = self.clkin,
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i_STDBY = self.stdby,
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o_LOCK = locked,
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p_FEEDBK_PATH = "INT_O{}".format(n_to_l[config['clkfb']]),
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p_FEEDBK_PATH = f"INT_O{n_to_l[config['clkfb']]}",
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p_CLKFB_DIV = config["clkfb_div"],
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p_CLKI_DIV = config["clki_div"]
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)
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self.comb += self.locked.eq(locked & ~self.reset)
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for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
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div = config["clko{}_div".format(n)]
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div = config[f"clko{n}_div"]
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cphase = int(p*(div + 1)/360 + div - 1)
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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self.params["p_CLKO{}_DIV".format(n_to_l[n])] = div
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self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0
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self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = cphase
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self.params["o_CLKO{}".format(n_to_l[n])] = clk
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self.params[f"p_CLKO{n_to_l[n]}_ENABLE"] = "ENABLED"
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self.params[f"p_CLKO{n_to_l[n]}_DIV"] = div
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self.params[f"p_CLKO{n_to_l[n]}_FPHASE"] = 0
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self.params[f"p_CLKO{n_to_l[n]}_CPHASE"] = cphase
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self.params[f"o_CLKO{n_to_l[n]}"] = clk
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self.specials += Instance("EHXPLLL", **self.params)
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@ -116,7 +116,7 @@ class TestClock(unittest.TestCase):
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def test_ecp5pll(self):
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pll = ECP5PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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for i in range(pll.nclkouts_max-1):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6, uses_dpa=(i != 0))
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pll.expose_dpa()
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pll.compute_config()
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