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mibuild: support multiple specifications of include file and sources

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This commit is contained in:
Sebastien Bourdeauducq 2015-04-04 18:58:02 +08:00
parent 357c807eb1
commit 1d1189506a
4 changed files with 7 additions and 7 deletions
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2
mibuild/altera/quartus.py
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@ -85,7 +85,7 @@ class AlteraQuartusToolchain:
named_sc, named_pc = platform.resolve_signals(vns) named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v" v_file = build_name + ".v"
tools.write_to_file(v_file, v_src) tools.write_to_file(v_file, v_src)
sources = platform.sources + [(v_file, "verilog")] sources = platform.sources | {(v_file, "verilog")}
_build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name) _build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name)
if run: if run:
_run_quartus(build_name, quartus_path) _run_quartus(build_name, quartus_path)

8
mibuild/generic_platform.py
View file

@ -184,8 +184,8 @@ class GenericPlatform:
if name is None: if name is None:
name = self.__module__.split(".")[-1] name = self.__module__.split(".")[-1]
self.name = name self.name = name
self.sources = [] self.sources = set()
self.verilog_include_paths = [] self.verilog_include_paths = set()
self.finalized = False self.finalized = False
def request(self, *args, **kwargs): def request(self, *args, **kwargs):
@ -229,7 +229,7 @@ class GenericPlatform:
if language is None: if language is None:
language = "verilog" # default to Verilog language = "verilog" # default to Verilog
filename = os.path.abspath(filename) filename = os.path.abspath(filename)
self.sources.append((filename, language)) self.sources.add((filename, language))
def add_sources(self, path, *filenames, language=None): def add_sources(self, path, *filenames, language=None):
for f in filenames: for f in filenames:
@ -251,7 +251,7 @@ class GenericPlatform:
self.add_source(filename, language) self.add_source(filename, language)
def add_verilog_include_path(self, path): def add_verilog_include_path(self, path):
self.verilog_include_paths.append(os.path.abspath(path)) self.verilog_include_paths.add(os.path.abspath(path))
def resolve_signals(self, vns): def resolve_signals(self, vns):
# resolve signal names in constraints # resolve signal names in constraints

2
mibuild/xilinx/ise.py
View file

@ -149,7 +149,7 @@ class XilinxISEToolchain:
named_sc, named_pc = platform.resolve_signals(vns) named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v" v_file = build_name + ".v"
tools.write_to_file(v_file, v_src) tools.write_to_file(v_file, v_src)
sources = platform.sources + [(v_file, "verilog")] sources = platform.sources | {(v_file, "verilog")}
if mode == "xst": if mode == "xst":
_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt) _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
isemode = "xst" isemode = "xst"

2
mibuild/xilinx/vivado.py
View file

@ -110,7 +110,7 @@ class XilinxVivadoToolchain:
named_sc, named_pc = platform.resolve_signals(vns) named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v" v_file = build_name + ".v"
tools.write_to_file(v_file, v_src) tools.write_to_file(v_file, v_src)
sources = platform.sources + [(v_file, "verilog")] sources = platform.sources | {(v_file, "verilog")}
_build_files(platform.device, sources, platform.verilog_include_paths, build_name, _build_files(platform.device, sources, platform.verilog_include_paths, build_name,
self.bitstream_commands, self.additional_commands) self.bitstream_commands, self.additional_commands)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc)) tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))