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cores/gpio: Simplify #1035.

This commit is contained in:
Florent Kermarrec 2021-09-20 17:34:46 +02:00
parent 6251474b39
commit 1e24fd87d1
1 changed files with 7 additions and 13 deletions
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20
litex/soc/cores/gpio.py
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@ -74,16 +74,16 @@ class GPIOInOut(Module):
class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
def __init__(self, pads, with_irq=False):
assert isinstance(pads, Signal) or isinstance(pads, Record)
nbits = len(pads) if isinstance(pads, Signal) else len(pads.o)
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
# # #
if isinstance(pads, Signal):
# Proper inout IOs
nbits = len(pads)
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
# Proper inout IOs.
for i in range(nbits):
t = TSTriple()
self.specials += t.get_tristate(pads[i])
@ -91,13 +91,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
self.comb += t.o.eq(self._out.storage[i])
self.specials += MultiReg(t.i, self._in.status[i])
else:
# Tristate record, for external tristate IO chips or simulation
nbits = len(pads.oe)
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
clocked_inputs = Signal.like(pads.i)
# Tristate inout IOs (For external tristate IO chips or simulation).
for i in range(nbits):
self.comb += pads.oe[i].eq(self._oe.storage[i])
self.comb += pads.o[i].eq(self._out.storage[i])