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build.py: use implicit get_fragment

This commit is contained in:
Sebastien Bourdeauducq 2013-03-12 16:13:20 +01:00
parent a23df42a7a
commit 1e7783a41e
1 changed files with 1 additions and 1 deletions
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2
build.py
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@ -58,7 +58,7 @@ NET "asfifo*/preset_empty*" TIG;
"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v") "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v") plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains()) plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
if __name__ == "__main__": if __name__ == "__main__":
main() main()