fhdl: do not attempt slicing non-array signals to keep Verilog happy
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@ -34,6 +34,12 @@ def _printexpr(ns, node):
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raise TypeError
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raise TypeError
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return "(" + r + ")"
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return "(" + r + ")"
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elif isinstance(node, _Slice):
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elif isinstance(node, _Slice):
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# Verilog does not like us slicing non-array signals...
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if isinstance(node.value, Signal) \
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and node.value.bv.width == 1 \
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and node.start == 0 and node.stop == 1:
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return _printexpr(ns, node.value)
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if node.start + 1 == node.stop:
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if node.start + 1 == node.stop:
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sr = "[" + str(node.start) + "]"
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sr = "[" + str(node.start) + "]"
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else:
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else:
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