soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing.

This commit is contained in:
Florent Kermarrec 2020-07-21 19:54:42 +02:00
parent 408d1a9f5d
commit 1f27b7405e
1 changed files with 4 additions and 1 deletions

View File

@ -1299,7 +1299,10 @@ class LiteXSoC(SoC):
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
self.bus.add_master("sdblock2mem", master=bus)
if hasattr(self.cpu, "dmabus"): # FIXME: VexRiscv SMP / DMA test.
self.submodules += wishbone.Converter(bus, self.cpu.dmabus)
else:
self.bus.add_master("sdblock2mem", master=bus)
self.add_csr("sdblock2mem")
# Mem2Block DMA