gen/fhdl/verilog: Improve _print_signal to align signals definition.
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@ -145,9 +145,12 @@ def _print_constant(node):
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# Print Signal -------------------------------------------------------------------------------------
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# Print Signal -------------------------------------------------------------------------------------
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def _print_signal(ns, s):
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def _print_signal(ns, s):
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length = 8
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vector = f"[{str(len(s)-1)}:0] "
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vector = " "*(length-len(vector)) + vector
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return "{signed}{vector}{name}".format(
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return "{signed}{vector}{name}".format(
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signed = " " if (not s.signed) else "signed ",
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signed = " " if (not s.signed) else "signed ",
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vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ",
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vector = " "*length if (len(s) <= 1) else vector,
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name = ns.get_name(s)
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name = ns.get_name(s)
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)
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)
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