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gen/fhdl/verilog: Improve _print_signal to align signals definition.

This commit is contained in:
Florent Kermarrec 2022-10-21 19:39:02 +02:00
parent b6e672a060
commit 1f58ce3c31
1 changed files with 5 additions and 2 deletions
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7
litex/gen/fhdl/verilog.py
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@ -145,9 +145,12 @@ def _print_constant(node):
# Print Signal ------------------------------------------------------------------------------------- # Print Signal -------------------------------------------------------------------------------------
def _print_signal(ns, s): def _print_signal(ns, s):
length = 8
vector = f"[{str(len(s)-1)}:0] "
vector = " "*(length-len(vector)) + vector
return "{signed}{vector}{name}".format( return "{signed}{vector}{name}".format(
signed = "" if (not s.signed) else "signed ", signed = " " if (not s.signed) else "signed ",
vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ", vector = " "*length if (len(s) <= 1) else vector,
name = ns.get_name(s) name = ns.get_name(s)
) )