add BUFIO to clockgen buffer options
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@ -59,6 +59,8 @@ class XilinxClocking(Module, AutoCSR):
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self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
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elif buf == "bufgce" and clk_ce != None:
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self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=clk_ce)
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elif buf == "bufio":
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self.specials += Instance("BUFIO", i_I=clkout, o_O=clkout_buf)
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else:
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raise ValueError
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