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soc: report System clock to 3dp

This commit is contained in:
Andrew Dennison 2021-10-15 09:39:06 +11:00
parent 0e164bb23c
commit 1fd99b366a
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -731,7 +731,7 @@ class SoC(Module):
self.logger.info(colorer("Creating SoC... ({})".format(build_time())))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info("FPGA device : {}.".format(platform.device))
self.logger.info("System clock: {:3.2f}MHz.".format(sys_clk_freq/1e6))
self.logger.info("System clock: {:3.3f}MHz.".format(sys_clk_freq/1e6))
# SoC attributes ---------------------------------------------------------------------------
self.platform = platform