vexriscv: verilog: pull debug-enabled verilog

The upstream vexriscv repo now generates both the current VexRiscv.v softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes their specialized debug bus that allows for attaching a modified version of openocd. Sync the litex repo with the upstream version to take advantage of debug support. Signed-off-by: Sean Cross <sean@xobs.io>
2018-06-28 09:24:34 +08:00 · 2018-06-28 09:24:34 +08:00 · 2024542a3c
parent fa0215660b
commit 2024542a3c
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@ -1 +1 @@
-Subproject commit 4811a12127eef5dfaaa8df47a59e58a1e561b0eb
+Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5