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cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.

This commit is contained in:
Florent Kermarrec 2024-11-05 16:46:23 +01:00
parent 0170462fe8
commit 20b0e98fe0
2 changed files with 17 additions and 36 deletions
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48
litex/soc/cores/cpu/urv/core.py
View File

@ -119,39 +119,25 @@ class uRV(CPU):
# uRV Instruction Bus. # uRV Instruction Bus.
# -------------------- # --------------------
if True: self.i_fsm = i_fsm = FSM(reset_state="IDLE")
from litex.soc.integration.common import get_mem_data i_fsm.act("IDLE",
self.rom = Memory(32, depth=131072//4) If(im_rd,
self.rom_port = self.rom.get_port() NextValue(im_valid, 0),
NextState("READ")
self.sync += im_valid.eq(1),
self.comb += [
self.rom_port.adr.eq(im_addr[2:]),
im_data.eq(self.rom_port.dat_r),
]
else:
# FIXME: Try to implement im_bus -> Wishbone correctly (if possible).
im_addr_d = Signal(32, reset=0xffffffff)
self.sync += im_addr_d.eq(im_addr)
self.i_fsm = i_fsm = FSM(reset_state="IDLE")
i_fsm.act("IDLE",
If(im_addr != im_addr_d,
NextValue(im_valid, 0),
NextState("READ")
)
) )
i_fsm.act("READ", )
ibus.stb.eq(1), i_fsm.act("READ",
ibus.cyc.eq(1), ibus.stb.eq(1),
ibus.we.eq(0), ibus.cyc.eq(1),
ibus.adr.eq(im_addr), ibus.we.eq(0),
ibus.sel.eq(0b1111), ibus.adr.eq(im_addr),
If(ibus.ack, ibus.sel.eq(0b1111),
NextValue(im_valid, 1), If(ibus.ack,
NextValue(im_data, ibus.dat_r), NextValue(im_valid, 1),
NextState("IDLE") NextValue(im_data, ibus.dat_r),
) NextState("IDLE")
) )
)
# uRV Data Bus. # uRV Data Bus.
# ------------- # -------------

5
litex/soc/integration/builder.py
View File

@ -339,11 +339,6 @@ class Builder:
# Initialize SoC with with BIOS data. # Initialize SoC with with BIOS data.
self.soc.init_rom(name="rom", contents=bios_data) self.soc.init_rom(name="rom", contents=bios_data)
# FIXME: Remove uRV ROM Init Workaround.
from litex.soc.cores.cpu.urv import uRV
if isinstance(self.soc.cpu, uRV):
self.soc.cpu.rom.init = bios_data
def build(self, **kwargs): def build(self, **kwargs):
# Pass Output Directory to Platform. # Pass Output Directory to Platform.
self.soc.platform.output_dir = self.output_dir self.soc.platform.output_dir = self.output_dir