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examples/pytholite/uio: simulate and convert Pytholite

This commit is contained in:
Sebastien Bourdeauducq 2012-11-23 13:10:40 +01:00
parent 4c216d8f11
commit 20d87682ad
1 changed files with 10 additions and 7 deletions
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17
examples/pytholite/uio.py
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@ -13,8 +13,9 @@ layout = [("r", BV(32))]
def gen(): def gen():
ds = Register(32) ds = Register(32)
for i in range(10): for i in range(5):
r = TRead(i) # NB: busname is optional when only one bus is configured
r = TRead(i, busname="wb")
yield r yield r
ds.store = r.data ds.store = r.data
yield Token("result", {"r": ds}) yield Token("result", {"r": ds})
@ -55,11 +56,13 @@ def main():
buses={"wb": wishbone.Interface()}) buses={"wb": wishbone.Interface()})
run_sim(ng_native) run_sim(ng_native)
#print("Simulating Pytholite:") print("Simulating Pytholite:")
#ng_pytholite = make_pytholite(gen, dataflow=[("result", Source, layout)]) ng_pytholite = make_pytholite(gen,
#run_sim(ng_pytholite) dataflow=[("result", Source, layout)],
buses={"wb": wishbone.Interface()})
run_sim(ng_pytholite)
#print("Converting Pytholite to Verilog:") print("Converting Pytholite to Verilog:")
#print(verilog.convert(ng_pytholite.get_fragment())) print(verilog.convert(ng_pytholite.get_fragment()))
main() main()