vexii/naxii fix floating axi wires

2024-05-20 08:55:05 +02:00 · 2024-05-20 08:55:05 +02:00 · 21e0ec7f98
parent 5eeb999694
commit 21e0ec7f98
1 changed files with 10 additions and 0 deletions
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@ -439,6 +439,16 @@ class VexiiRiscv(CPU):
        )
        self.memory_buses.append(mbus)

+        self.comb += mbus.aw.cache.eq(0xF)
+        self.comb += mbus.aw.lock.eq(0)
+        self.comb += mbus.aw.prot.eq(1)
+        self.comb += mbus.aw.qos.eq(0)
+
+        self.comb += mbus.ar.cache.eq(0xF)
+        self.comb += mbus.ar.lock.eq(0)
+        self.comb += mbus.ar.prot.eq(1)
+        self.comb += mbus.ar.qos.eq(0)
+
        self.cpu_params.update(
            # Memory Bus (Master).
            # --------------------