soc_zynq: add missing axi hp0 clock

2019-07-10 16:51:08 +02:00 · 2019-07-10 16:51:08 +02:00 · 220f43753b
parent 9c8c037108
commit 220f43753b
1 changed files with 3 additions and 0 deletions
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@ -138,6 +138,9 @@ class SoCZynq(SoCCore):
        self.axi_hp0 = axi_hp0 = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
        self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
        self.ps7_params.update(
+            # axi hp0 clk
+            i_M_AXI_HP0_ACLK=ClockSignal("sys"),
+
            # axi hp0 aw
            i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,
            o_S_AXI_HP0_AWREADY=axi_hp0.aw.ready,