Add tests for FIFOSyncMacro
This commit is contained in:
Robert Szczepanski
parent
c584cb3fa7
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22abe1d543
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.ram.xilinx_fifo_sync_macro import FIFOSyncMacro
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class TestFIFOSyncMacro(unittest.TestCase):
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def testWriteRead(self):
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def generator(dut):
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# Check initial status
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yield
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self.assertEqual((yield dut.almostempty), 1)
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self.assertEqual((yield dut.empty), 1)
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self.assertEqual((yield dut.almostfull), 0)
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self.assertEqual((yield dut.full), 0)
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# Load values into FIFO
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for i in range(100):
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yield dut.wren.eq(1)
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yield dut.wr_d.eq(i)
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yield
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while (yield dut.fifo.sink.ready) == 0:
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yield
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yield dut.wren.eq(0)
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yield
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# Check if values are queued
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self.assertEqual((yield dut.wrcount), 100)
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self.assertEqual((yield dut.rdcount), 0)
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self.assertEqual((yield dut.almostempty), 1)
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self.assertEqual((yield dut.empty), 0)
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self.assertEqual((yield dut.almostfull), 0)
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self.assertEqual((yield dut.full), 0)
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# Read and check values
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for i in range(100):
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yield dut.rden.eq(1)
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yield
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self.assertEqual((yield dut.rd_d), i)
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yield dut.rden.eq(0)
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yield
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# Check if status is updated
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self.assertEqual((yield dut.wrcount), 100)
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self.assertEqual((yield dut.rdcount), 100)
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self.assertEqual((yield dut.almostempty), 1)
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self.assertEqual((yield dut.empty), 1)
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self.assertEqual((yield dut.almostfull), 0)
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self.assertEqual((yield dut.full), 0)
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dut = FIFOSyncMacro("18Kb", data_width=32, almost_empty_offset=128,
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almost_full_offset=128, toolchain="symbiflow")
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run_simulation(dut, generator(dut))
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def testWrRdErrors(self):
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def generator(dut):
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# Load values into FIFO
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for i in range(500):
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yield dut.wren.eq(1)
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yield dut.wr_d.eq(i)
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yield
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while (yield dut.fifo.sink.ready) == 0:
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yield
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yield dut.wren.eq(0)
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yield
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# Check if values are queued
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self.assertEqual((yield dut.wrcount), 500)
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self.assertEqual((yield dut.rdcount), 0)
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self.assertEqual((yield dut.almostempty), 0)
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self.assertEqual((yield dut.empty), 0)
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self.assertEqual((yield dut.almostfull), 1)
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self.assertEqual((yield dut.full), 0)
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self.assertEqual((yield dut.wrerr), 0)
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self.assertEqual((yield dut.rderr), 0)
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# Load to queue 511 values since the next one will overflow wrcount
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for i in range(11):
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yield dut.wren.eq(1)
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yield dut.wr_d.eq(500 + i)
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yield
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while (yield dut.fifo.sink.ready) == 0:
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yield
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self.assertEqual((yield dut.wrcount), 500 + i)
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yield dut.wren.eq(0)
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yield
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self.assertEqual((yield dut.wrcount), 511)
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# Next load should overflow wrcount and make FIFO full
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yield dut.wren.eq(1)
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yield dut.wr_d.eq(511)
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yield
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while (yield dut.fifo.sink.ready) == 0:
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yield
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yield dut.wren.eq(0)
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yield
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self.assertEqual((yield dut.wrcount), 0)
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self.assertEqual((yield dut.almostfull), 1)
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self.assertEqual((yield dut.full), 1)
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self.assertEqual((yield dut.wrerr), 0)
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# Every next load should cause wrerr assert since FIFO is already full
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yield dut.wren.eq(1)
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yield dut.wr_d.eq(512)
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yield
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# Check if status is updated
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self.assertEqual((yield dut.wrcount), 0)
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self.assertEqual((yield dut.rdcount), 0)
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self.assertEqual((yield dut.almostempty), 0)
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self.assertEqual((yield dut.empty), 0)
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self.assertEqual((yield dut.almostfull), 1)
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self.assertEqual((yield dut.full), 1)
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self.assertEqual((yield dut.wrerr), 1)
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self.assertEqual((yield dut.rderr), 0)
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yield dut.wren.eq(0)
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yield
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# Read values until max rdcount
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for i in range(511):
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yield dut.rden.eq(1)
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yield
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while (yield dut.fifo.source.valid) == 0:
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yield
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self.assertEqual((yield dut.rd_d), i)
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yield dut.rden.eq(0)
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yield
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self.assertEqual((yield dut.rdcount), 511)
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self.assertEqual((yield dut.almostempty), 1)
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# Next read should make FIFO empty
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yield dut.rden.eq(1)
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yield
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yield dut.rden.eq(0)
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yield
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self.assertEqual((yield dut.almostempty), 1)
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self.assertEqual((yield dut.empty), 1)
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# FIFO is empty so every next read should cause rderr assert
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yield dut.rden.eq(1)
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yield
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# Check if status is updated
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self.assertEqual((yield dut.wrcount), 0)
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self.assertEqual((yield dut.rdcount), 0)
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self.assertEqual((yield dut.almostempty), 1)
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self.assertEqual((yield dut.empty), 1)
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self.assertEqual((yield dut.almostfull), 0)
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self.assertEqual((yield dut.full), 0)
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self.assertEqual((yield dut.wrerr), 0)
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self.assertEqual((yield dut.rderr), 1)
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dut = FIFOSyncMacro("18Kb", data_width=32, almost_empty_offset=128,
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almost_full_offset=128, toolchain="symbiflow")
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run_simulation(dut, generator(dut))
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