Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO
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Robert Szczepanski
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ca6378a207
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from migen import *
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from litex.soc.interconnect.stream import SyncFIFO
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class FIFOSyncMacro(Module, Record):
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"""FIFOSyncMacro
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Provides an equivalent of Xilinx' FIFO_SYNC_MACRO which is a unimacro dedicated for 7 series
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FPGAs and Zynq-7000 SoC.
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Detailed informations can be found in official documentation:
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https://docs.xilinx.com/r/2021.2-English/ug953-vivado-7series-libraries/FIFO_SYNC_MACRO
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"""
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def __init__(self, fifo_size="18Kb", data_width=32, almost_empty_offset=0, almost_full_offset=0, do_reg=0, toolchain="vivado"):
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assert data_width <= 72
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assert fifo_size in ["18Kb", "36Kb"]
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if do_reg and toolchain != "vivado":
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raise NotImplementedError("FIFOSyncMacro: DO_REG==1 is supported only for Vivado toolchain")
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fifo_sync_macro_layout = [
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("rd_d", data_width),
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("almostfull", 1),
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("almostempty", 1),
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("full", 1),
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("empty", 1),
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("rdcount", 13),
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("rderr", 1),
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("wrerr", 1),
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("wrcount", 13),
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("rden", 1),
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("wr_d", data_width),
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("wren", 1),
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("reset", 1)
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]
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Record.__init__(self, fifo_sync_macro_layout)
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if toolchain == "vivado":
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self.specials += Instance("FIFO_SYNC_MACRO",
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p_DEVICE = "7SERIES",
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p_FIFO_SIZE = fifo_size,
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p_DATA_WIDTH = data_width,
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p_ALMOST_EMPTY_OFFSET = almost_empty_offset,
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p_ALMOST_FULL_OFFSET = almost_full_offset,
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p_DO_REG = do_reg,
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i_CLK = ClockSignal(),
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i_RST = self.reset,
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o_ALMOSTFULL = self.almostfull,
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o_ALMOSTEMPTY = self.almostempty,
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o_FULL = self.full,
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o_EMPTY = self.empty,
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i_WREN = self.wren,
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i_DI = self.wr_d,
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i_RDEN = self.rden,
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o_DO = self.rd_d,
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o_RDCOUNT = self.rdcount,
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o_RDERR = self.rderr,
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o_WRCOUNT = self.wrcount,
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o_WRERR = self.wrerr,
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)
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else:
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level = Signal(14)
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# FIFO size is adjusted to only match configurations supported by FIFO_SYNC_MACRO
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if fifo_size == "18Kb":
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fifo_size = 16
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elif fifo_size == "36Kb":
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fifo_size = 32
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else:
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raise ValueError("FIFOSyncMacro can only be configured to 18Kb or 36Kb of memory")
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if data_width in range(1, 5):
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macro_data_width = 4
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elif data_width in range(5, 10):
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macro_data_width = 8
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elif data_width in range(10, 19):
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macro_data_width = 16
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elif data_width in range(19, 37):
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macro_data_width = 32
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elif data_width in range(37, 73):
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if fifo_size == 36:
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macro_data_width = 64
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else:
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raise ValueError("FIFOSyncMacro accepts data width up to 72 bits only for 36Kb FIFO size.")
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else:
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raise ValueError("FIFOSyncMacro only accepts data width up to 72 bits.")
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self.fifo_depth = fifo_depth = (int)(fifo_size * 1024 / macro_data_width)
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self.submodules.fifo = fifo = ResetInserter()(SyncFIFO([("data", data_width)], fifo_depth))
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self.comb += [
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fifo.reset.eq(self.reset),
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level.eq(fifo.level),
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# connect port signals to internal fifo
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# sink
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fifo.sink.data.eq(self.wr_d),
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fifo.sink.valid.eq(self.wren),
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# source
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self.rd_d.eq(fifo.source.data),
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fifo.source.ready.eq(self.rden),
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self.wrerr.eq(~fifo.sink.ready & self.wren),
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self.rderr.eq(fifo.source.ready & self.rden),
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If(level == 0,
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self.empty.eq(1)
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).Else(
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self.empty.eq(0)
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),
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If(level == fifo_depth,
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self.full.eq(1)
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).Else(
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self.full.eq(0)
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),
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]
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self.sync += [
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# reset only these two since other signals are dependent on fifo state
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If(self.reset,
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self.rdcount.eq(0),
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self.wrcount.eq(0),
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),
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# wrcount and rdcount are counters of respectively written and read words
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If(fifo.sink.ready & fifo.sink.valid,
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If(self.wrcount == (fifo_depth - 1),
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self.wrcount.eq(0)
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).Else(
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self.wrcount.eq(self.wrcount + 1),
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)
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),
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If(fifo.source.ready & fifo.source.valid,
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If(self.rdcount == (fifo_depth - 1),
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self.rdcount.eq(0)
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).Else(
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self.rdcount.eq(self.rdcount + 1),
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)
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),
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# assert almostempty when fifo level is lower than almost_empty_offset
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If((level <= almost_empty_offset),
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self.almostempty.eq(1)
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).Else(
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self.almostempty.eq(0)
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),
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# assert almostfull when fifo level is higher than almost_full_offset
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If((level >= (fifo_depth - almost_full_offset)),
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self.almostfull.eq(1)
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).Else(
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self.almostfull.eq(0)
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),
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]
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