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Merge pull request #1949 from alexey-morozov/master 

The case when AWVALID and WVALID are not asserted at the same cycle
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enjoy-digital 2024-06-23 09:03:17 +02:00 committed by GitHub
parent dd01a87653 903c5fb9a1
commit 22f9c063db
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1 changed files with 14 additions and 0 deletions
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14
litex/soc/interconnect/axi/axi_lite.py
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@ -168,6 +168,8 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=
else: else:
comb.append(port_we.eq(axi_lite.w.valid & axi_lite.w.ready & (axi_lite.w.strb != 0))) comb.append(port_we.eq(axi_lite.w.valid & axi_lite.w.ready & (axi_lite.w.strb != 0)))
port_adr_reg = Signal(len(port_adr))
fsm = FSM() fsm = FSM()
fsm.act("START-TRANSACTION", fsm.act("START-TRANSACTION",
# If the last access was a read, do a write, and vice versa. # If the last access was a read, do a write, and vice versa.
@ -186,12 +188,24 @@ def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=
If(axi_lite.w.valid, If(axi_lite.w.valid,
axi_lite.w.ready.eq(1), axi_lite.w.ready.eq(1),
NextState("SEND-WRITE-RESPONSE") NextState("SEND-WRITE-RESPONSE")
).Else(
# write data is not yet available - register the address
# and wait until the master provides the data
NextValue(port_adr_reg, port_adr),
NextState("WAIT-FOR-WRITE-DATA")
) )
).Elif(do_read, ).Elif(do_read,
port_adr.eq(axi_lite.ar.addr[adr_shift:]), port_adr.eq(axi_lite.ar.addr[adr_shift:]),
NextState("LATCH-READ-RESPONSE"), NextState("LATCH-READ-RESPONSE"),
) )
) )
fsm.act("WAIT-FOR-WRITE-DATA",
port_adr.eq(port_adr_reg),
If(axi_lite.w.valid,
axi_lite.w.ready.eq(1),
NextState("SEND-WRITE-RESPONSE")
)
),
fsm.act("LATCH-READ-RESPONSE", fsm.act("LATCH-READ-RESPONSE",
NextValue(port_dat_r_latched, port_dat_r), NextValue(port_dat_r_latched, port_dat_r),
NextState("SEND-READ-RESPONSE") NextState("SEND-READ-RESPONSE")