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boards/targets: uniformize things between targets

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This commit is contained in:
Florent Kermarrec 2018-09-24 10:58:10 +02:00
parent 01b025aafd
commit 22febe9582
9 changed files with 67 additions and 62 deletions
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7
litex/boards/targets/arty.py
View file

@ -99,7 +99,8 @@ class BaseSoC(SoCSDRAM):
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, **kwargs):
platform = arty.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=100*1000000,
sys_clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
@ -107,8 +108,8 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)

15
litex/boards/targets/de0nano.py
View file

@ -13,12 +13,13 @@ from litedram.modules import IS42S16160
from litedram.phy import GENSDRPHY
class _PLL(Module):
class _ALTPLL(Module):
def __init__(self, period_in, name, phase_shift, operation_mode):
self.clk_in = Signal()
self.clk_out = Signal()
self.specials += Instance("ALTPLL",
self.specials += \
Instance("ALTPLL",
p_bandwidth_type = "AUTO",
p_clk0_divide_by = 1,
p_clk0_duty_cycle = 50,
@ -60,14 +61,14 @@ class _CRG(Module):
clk50 = platform.request("clk50")
sys_pll = _PLL(20, "sys", 0, "NORMAL")
sys_pll = _ALTPLL(20, "sys", 0, "NORMAL")
self.submodules += sys_pll
self.comb += [
sys_pll.clk_in.eq(clk50),
self.cd_sys.clk.eq(sys_pll.clk_out)
]
sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
sdram_pll = _ALTPLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
self.submodules += sdram_pll
self.comb += [
sdram_pll.clk_in.eq(clk50),
@ -89,15 +90,15 @@ class _CRG(Module):
class BaseSoC(SoCSDRAM):
def __init__(self, **kwargs):
platform = de0nano.Platform()
SoCSDRAM.__init__(self, platform,
clk_freq=100*1000000,
sys_clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,

5
litex/boards/targets/genesys2.py
View file

@ -81,7 +81,8 @@ class BaseSoC(SoCSDRAM):
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, **kwargs):
platform = genesys2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=125*1000000,
sys_clk_freq = int(125e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
@ -89,7 +90,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"))
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,

7
litex/boards/targets/kc705.py
View file

@ -81,7 +81,8 @@ class BaseSoC(SoCSDRAM):
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, **kwargs):
platform = kc705.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=125*1000000,
sys_clk_freq = int(125e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
@ -89,8 +90,8 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)

8
litex/boards/targets/minispartan6.py
View file

@ -68,17 +68,17 @@ class _CRG(Module):
class BaseSoC(SoCSDRAM):
def __init__(self, **kwargs):
clk_freq = 80*1000000
platform = minispartan6.Platform()
SoCSDRAM.__init__(self, platform, clk_freq,
sys_clk_freq = int(80e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(clk_freq, "1:1")
sdram_module = AS4C16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)

2
litex/boards/targets/nexys4ddr.py
View file

@ -95,7 +95,7 @@ class BaseSoC(SoCSDRAM):
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq)
sdram_module = MT47H64M16(self.clk_freq, "1:2")
sdram_module = MT47H64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)

7
litex/boards/targets/nexys_video.py
View file

@ -88,7 +88,8 @@ class BaseSoC(SoCSDRAM):
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, **kwargs):
platform = nexys_video.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=100*1000000,
sys_clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
@ -96,8 +97,8 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
sdram_module = MT41K256M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)

12
litex/boards/targets/sim.py
View file

@ -63,8 +63,8 @@ class SimSoC(SoCSDRAM):
with_analyzer=False,
**kwargs):
platform = sim.Platform()
SoCSDRAM.__init__(self, platform,
clk_freq=int(1e9/platform.default_clk_period),
sys_clk_freq = int(1e9/platform.default_clk_period)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
ident="LiteX Simulation", ident_version=True,
with_uart=False,
@ -78,7 +78,7 @@ class SimSoC(SoCSDRAM):
# sdram
if with_sdram:
sdram_module = IS42S16160(self.clk_freq, "1:1")
sdram_module = IS42S16160(sys_clk_freq, "1:1")
phy_settings = PhySettings(
memtype="SDR",
dfi_databits=1*16,
@ -122,7 +122,7 @@ class SimSoC(SoCSDRAM):
self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
# eth core
etherbonecore = LiteEthUDPIPCore(self.etherbonephy,
etherbone_mac_address, convert_ip(etherbone_ip_address), self.clk_freq)
etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq)
if with_ethernet:
etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore)
self.submodules.etherbonecore = etherbonecore
@ -134,8 +134,8 @@ class SimSoC(SoCSDRAM):
if with_analyzer:
analyzer_signals = [
# FIXME: find interesting signals to probe
self.cpu_or_bridge.ibus,
self.cpu_or_bridge.dbus
self.cpu.ibus,
self.cpu.dbus
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)

4
litex/boards/targets/simple.py
View file

@ -14,8 +14,8 @@ from liteeth.core.mac import LiteEthMAC
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
SoCCore.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
sys_clk_freq = int(1e9/platform.default_clk_period)
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024,
**kwargs)