cores/uart: add UARTCrossover

This commit is contained in:
Florent Kermarrec 2020-01-13 10:14:38 +01:00
parent 2f03d3234e
commit 23175190d8
2 changed files with 17 additions and 0 deletions

View File

@ -264,3 +264,18 @@ class UARTMultiplexer(Module):
uarts[n].rx.eq(uart.rx)
]
self.comb += Case(self.sel, cases)
# UART Crossover -----------------------------------------------------------------------------------
class UARTCrossover(UART):
"""
UART crossover trough Wishbone bridge.
Creates a fully compatible UART that can be used by the CPU as a regular UART and adds a second
UART, cross-connected to the main one to allow terminal emulation over a Wishbone bridge.
"""
def __init__(self, **kwargs):
assert kwargs.get("phy", None) == None
UART.__init__(self, **kwargs)
self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
self.comb += self.connect(self.xover)

View File

@ -243,6 +243,8 @@ class SoCCore(Module):
self.submodules.uart = uart.UART()
if uart_name == "stub":
self.comb += uart.sink.ready.eq(1)
elif uart_name == "crossover":
self.submodules.uart = uart.UARTCrossover()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic