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soc/cores/clock/efinix: fix input clock code for trion when the input clock comes from another PLL

This commit is contained in:
Gwenhael Goavec-Merou 2024-01-25 17:39:12 +01:00
parent d32095540a
commit 245bed7195
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/clock/efinix.py
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@ -88,7 +88,7 @@ class EFINIXPLL(LiteXModule):
self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no)) self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
self.platform.get_pll_resource(pll_res) self.platform.get_pll_resource(pll_res)
else: else:
block["input_clock"] = "INTERNAL" block["input_clock"] = "INTERNAL" if self.type == "TITANIUMPLL" else "CORE"
block["resource"] = self.platform.get_free_pll_resource() block["resource"] = self.platform.get_free_pll_resource()
block["input_signal"] = name block["input_signal"] = name
self.logger.info("Clock source: {}".format(block["input_clock"])) self.logger.info("Clock source: {}".format(block["input_clock"]))