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soc/cores/clock: add Cyclone10LPPLL.

This commit is contained in:
Florent Kermarrec 2020-04-08 08:33:57 +02:00
parent f8d6d0fda8
commit 2470ef5096
1 changed files with 28 additions and 0 deletions
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28
litex/soc/cores/clock.py
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@ -856,3 +856,31 @@ class CycloneVPLL(IntelClocking):
"-C8" : (0e6, 460e6), "-C8" : (0e6, 460e6),
"-A7" : (0e6, 460e6), "-A7" : (0e6, 460e6),
}[speedgrade] }[speedgrade]
# Intel / Cyclone10LP ------------------------------------------------------------------------------
class Cyclone10LPPLL(IntelClocking):
nclkouts_max = 5
n_div_range = (1, 512+1)
m_div_range = (1, 512+1)
c_div_range = (1, 512+1)
clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use
vco_freq_range = (600e6, 1300e6)
def __init__(self, speedgrade="-C6"):
self.logger = logging.getLogger("Cyclone10LPPLL")
self.logger.info("Creating Cyclone10LPPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
IntelClocking.__init__(self)
self.clkin_freq_range = {
"-C6" : (5e6, 472.5e6),
"-C8" : (5e6, 472.5e6),
"-I7" : (5e6, 472.5e6),
"-A7" : (5e6, 472.5e6),
"-I8" : (5e6, 362e6),
}[speedgrade]
self.clko_freq_range = {
"-C6" : (0e6, 472.5e6),
"-C8" : (0e6, 402.5e6),
"-I7" : (0e6, 450e6),
"-A7" : (0e6, 450e6),
"-I8" : (0e6, 362e6),
}[speedgrade]