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Merge pull request #1325 from AEW2015/litex_dev 

adding JTAG support for the xcau, Xilinx Artix UltraScale+
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enjoy-digital 2022-06-07 12:11:57 +02:00 committed by GitHub
parent 50613f74c0 9691d205b7
commit 24e483026d
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litex/soc/cores/jtag.py
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@ -307,7 +307,7 @@ class XilinxJTAG(Module):
prim_dict = { prim_dict = {
# Primitive Name Ðevice (startswith) # Primitive Name Ðevice (startswith)
"BSCAN_SPARTAN6" : ["xc6"], "BSCAN_SPARTAN6" : ["xc6"],
"BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcku", "xcvu", "xczu"], "BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcau", "xcku", "xcvu", "xczu"],
} }
for prim, prim_devs in prim_dict.items(): for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs: for prim_dev in prim_devs: