Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1325 from AEW2015/litex_dev 

adding JTAG support for the xcau, Xilinx Artix UltraScale+
This commit is contained in:
enjoy-digital 2022-06-07 12:11:57 +02:00 committed by GitHub
parent 50613f74c0 9691d205b7
commit 24e483026d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/jtag.py
View File

@ -307,7 +307,7 @@ class XilinxJTAG(Module):
prim_dict = {
# Primitive Name Ðevice (startswith)
"BSCAN_SPARTAN6" : ["xc6"],
"BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcku", "xcvu", "xczu"],
"BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcau", "xcku", "xcvu", "xczu"],
}
for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs: