Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

fix FemtoRV reset signal

Browse source
This commit is contained in:
Andy Kitchen 2021-11-25 22:36:52 +11:00
parent 85d6cb4b8d
commit 2562ae5f63
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/cores/cpu/femtorv/core.py
View file

@ -95,7 +95,7 @@ class FemtoRV(CPU):
# Clk / Rst.
i_clk = ClockSignal("sys"),
i_reset = ~ResetSignal("sys"), # Active Low.
i_reset = ~(ResetSignal("sys") | self.reset), # Active Low.
# I/D Bus.
o_mem_addr = mbus.addr,