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decorators: remove deprecated semantics

This commit is contained in:
Robert Jordens 2015-04-05 03:49:07 -06:00 committed by Sebastien Bourdeauducq
parent 8798ee8d73
commit 25e4d2a2db
3 changed files with 11 additions and 11 deletions
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4
examples/basic/two_dividers.py
View File

@ -2,8 +2,8 @@ from migen.fhdl.std import *
from migen.fhdl import verilog from migen.fhdl import verilog
from migen.genlib import divider from migen.genlib import divider
@DecorateModule(InsertReset) @ResetInserter()
@DecorateModule(InsertCE) @CEInserter()
class Example(Module): class Example(Module):
def __init__(self, width): def __init__(self, width):
d1 = divider.Divider(width) d1 = divider.Divider(width)

6
migen/genlib/fifo.py
View File

@ -158,7 +158,7 @@ class AsyncFIFO(Module, _FIFOInterface):
"""Asynchronous FIFO (first in, first out) """Asynchronous FIFO (first in, first out)
Read and write interfaces are accessed from different clock domains, Read and write interfaces are accessed from different clock domains,
named `read` and `write`. Use `RenameClockDomains` to rename to named `read` and `write`. Use `ClockDomainsRenamer` to rename to
other names. other names.
{interface} {interface}
@ -172,8 +172,8 @@ class AsyncFIFO(Module, _FIFOInterface):
depth_bits = log2_int(depth, True) depth_bits = log2_int(depth, True)
produce = RenameClockDomains(GrayCounter(depth_bits+1), "write") produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits+1))
consume = RenameClockDomains(GrayCounter(depth_bits+1), "read") consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits+1))
self.submodules += produce, consume self.submodules += produce, consume
self.comb += [ self.comb += [
produce.ce.eq(self.writable & self.we), produce.ce.eq(self.writable & self.we),

12
migen/genlib/misc.py
View File

@ -86,24 +86,24 @@ def timeline(trigger, events):
sync.append(counterlogic) sync.append(counterlogic)
return sync return sync
@DecorateModule(InsertReset) @ResetInserter()
@DecorateModule(InsertCE) @CEInserter()
class FlipFlop(Module): class FlipFlop(Module):
def __init__(self, *args, **kwargs): def __init__(self, *args, **kwargs):
self.d = Signal(*args, **kwargs) self.d = Signal(*args, **kwargs)
self.q = Signal(*args, **kwargs) self.q = Signal(*args, **kwargs)
self.sync += self.q.eq(self.d) self.sync += self.q.eq(self.d)
@DecorateModule(InsertReset) @ResetInserter()
@DecorateModule(InsertCE) @CEInserter()
class Counter(Module): class Counter(Module):
def __init__(self, *args, increment=1, **kwargs): def __init__(self, *args, increment=1, **kwargs):
self.value = Signal(*args, **kwargs) self.value = Signal(*args, **kwargs)
self.width = flen(self.value) self.width = flen(self.value)
self.sync += self.value.eq(self.value+increment) self.sync += self.value.eq(self.value+increment)
@DecorateModule(InsertReset) @ResetInserter()
@DecorateModule(InsertCE) @CEInserter()
class Timeout(Module): class Timeout(Module):
def __init__(self, length): def __init__(self, length):
self.reached = Signal() self.reached = Signal()