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Add litex.gen.fhdl.verilog.VerilogTime to emit $time

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This commit is contained in:
Jevin Sweval 2022-06-02 16:04:58 -07:00
parent f33ea63278
commit 260577cae8
1 changed files with 14 additions and 0 deletions
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14
litex/gen/fhdl/verilog.py
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@ -133,6 +133,18 @@ _ieee_1800_2017_verilog_reserved_keywords = {
# EXPRESSIONS #
# ------------------------------------------------------------------------------------------------ #
# Stub for $time in Display() args -----------------------------------------------------------------
class VerilogTime:
"""Expression for $time in Display() statements
Example:
self.sync += If(state != old_state,
Display("time=%t old_state: %d state: %d", VerilogTime(), old_state, state)
)
"""
pass
# Print Constant -----------------------------------------------------------------------------------
def _print_constant(node):
@ -322,6 +334,8 @@ def _print_node(ns, at, level, node, target_filter=None):
s += ", "
if isinstance(arg, Signal):
s += ns.get_name(arg)
elif isinstance(arg, VerilogTime):
s += "$time"
else:
s += str(arg)
return "\t"*level + "$display(" + s + ");\n"