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soc/interconnect/stream: expose depth on SyncFIFO

This commit is contained in:
Florent Kermarrec 2017-10-30 22:56:09 +01:00
parent 876f3d2c8f
commit 2665a83288
1 changed files with 1 additions and 0 deletions
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litex/soc/interconnect/stream.py
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@ -99,6 +99,7 @@ class SyncFIFO(_FIFOWrapper):
self, self,
fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO, fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
layout, depth) layout, depth)
self.depth = self.fifo.depth
self.level = self.fifo.level self.level = self.fifo.level