s6ddrphy: style and other minor fixes

.gitignore

@@ -11,6 +11,7 @@ tools/flterm
 tools/mkmmimg
 tools/byteswap
 software/include/hw/csr.h
+software/include/hw/sdram_phy.h
 software/videomixer/dvisampler0.c
 software/videomixer/dvisampler0.h
 software/videomixer/dvisampler1.c

milkymist/cif.py

@@ -67,14 +67,13 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
 	return r
 
 def get_sdram_phy_header(sdram_phy):
-
 		if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
-			raise NotImplementedError("sdram phy header generator only supports SDR, DDR, LPDDR and DDR2")
+			raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
 
-		r = "#ifndef __HW_SDRAM_PHY_H\n#define __SDRAM_PHY_H\n"
+		r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
 		r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
 
-		r += "extern void cdelay(int i);\n"
+		r += "static void cdelay(int i);\n"
 
 		#
 		# commands_px functions
@@ -126,7 +125,7 @@ static void command_p{n}(int cmd)
 			return r
 
 
-		r += "static void init_sequence(void) {\n"
+		r += "static void init_sequence(void)\n{\n"
 
 		cl = sdram_phy.phy_settings.cl
 		

milkymist/s6ddrphy/__init__.py

@@ -18,7 +18,6 @@
 
 # Todo:
 #	- use CSR for bitslip?
-#   - move sdram clk generation to phy?
 
 from migen.fhdl.std import *
 from migen.bus.dfi import *
@@ -26,7 +25,6 @@ from migen.genlib.record import *
 
 class S6DDRPHY(Module):
 	def __init__(self, pads, phy_settings, bitslip):
-		
 		if phy_settings.type not in ["DDR", "LPDDR", "DDR2"]:
 			raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
 
@@ -48,8 +46,6 @@ class S6DDRPHY(Module):
 		# sdram_full_rd_clk : full rate sdram write clk
 		sd_sys = getattr(self.sync, "sys")
 		sd_sdram_half = getattr(self.sync, "sdram_half")
-		sd_sdram_full_wr = getattr(self.sync, "sdram_full_wr")
-		sd_sdram_full_rd = getattr(self.sync, "sdram_full_rd")
 
 		sys_clk = ClockSignal("sys")
 		sdram_half_clk = ClockSignal("sdram_half")
@@ -102,10 +98,10 @@ class S6DDRPHY(Module):
 		# 
 		# Bitslip
 		#
-		bitslip_cnt   = Signal(4)
+		bitslip_cnt = Signal(4)
 		bitslip_inc = Signal()
 
-		sd_sys +=[
+		sd_sys += [
 			If(bitslip_cnt==bitslip, 
 				bitslip_inc.eq(0)
 			).Else(
@@ -120,7 +116,10 @@ class S6DDRPHY(Module):
 		sdram_half_clk_n = Signal()
 		self.comb += sdram_half_clk_n.eq(~sdram_half_clk)
 
-		postamble, drive_dqs, dqs_t_d0, dqs_t_d1 = (Signal() for i in range(4))
+		postamble = Signal()
+		drive_dqs = Signal()
+		dqs_t_d0 = Signal()
+		dqs_t_d1 = Signal()
 
 		dqs_o = Signal(d//8) 
 		dqs_t = Signal(d//8)
@@ -131,7 +130,6 @@ class S6DDRPHY(Module):
 		]
 
 		for i in range(d//8):
-
 			# DQS output
 			self.specials += Instance("ODDR2",
 				Instance.Parameter("DDR_ALIGNMENT", "C1"),
@@ -182,28 +180,32 @@ class S6DDRPHY(Module):
 			for i in range(2*nphases)]
 
 		for n, phase in enumerate(self.dfi.phases):
-			self.comb +=[
+			self.comb += [
 				d_dfi[n].wrdata.eq(phase.wrdata),
 				d_dfi[n].wrdata_mask.eq(phase.wrdata_mask),
 				d_dfi[n].wrdata_en.eq(phase.wrdata_en),
 				d_dfi[n].rddata_en.eq(phase.rddata_en),
 			]
-			sd_sys +=[
-					d_dfi[nphases+n].wrdata.eq(phase.wrdata),
-					d_dfi[nphases+n].wrdata_mask.eq(phase.wrdata_mask)
+			sd_sys += [
+				d_dfi[nphases+n].wrdata.eq(phase.wrdata),
+				d_dfi[nphases+n].wrdata_mask.eq(phase.wrdata_mask)
 			]
 
 
-		drive_dq, drive_dq_n, d_drive_dq, d_drive_dq_n = (Signal() for i in range(4))
-		self.comb +=[
+		drive_dq = Signal()
+		drive_dq_n = Signal()
+		d_drive_dq = Signal()
+		d_drive_dq_n = Signal()
+		self.comb += [
 			drive_dq_n.eq(~drive_dq),
 			d_drive_dq_n.eq(~d_drive_dq)
 		]
 
-		dq_t, dq_o, dq_i = (Signal(d) for i in range(3))
+		dq_t = Signal(d)
+		dq_o = Signal(d)
+		dq_i = Signal(d)
 
 		for i in range(d):
-
 			# Data serializer
 			self.specials += Instance("OSERDES2",
 				Instance.Parameter("DATA_WIDTH", 4),
@@ -240,7 +242,7 @@ class S6DDRPHY(Module):
 				Instance.Output("SHIFTOUT2"),
 				Instance.Output("SHIFTOUT3"),
 				Instance.Output("SHIFTOUT4"),
-				)
+			)
 
 			# Data deserializer
 			self.specials += Instance("ISERDES2",
@@ -272,7 +274,7 @@ class S6DDRPHY(Module):
 				Instance.Output("VALID"),
 				Instance.Output("INCDEC"),
 				Instance.Output("SHIFTOUT")
-				)
+			)
 
 			# Data buffer
 			self.specials += Instance("IOBUF",
@@ -280,10 +282,9 @@ class S6DDRPHY(Module):
 				Instance.Output("O", dq_i[i]),
 				Instance.Input("T", dq_t[i]),
 				Instance.InOut("IO", pads.dq[i])
-				)
+			)
 
 		for i in range(d//8):
-
 			# Mask serializer
 			self.specials += Instance("OSERDES2",
 				Instance.Parameter("DATA_WIDTH", 4),
@@ -320,7 +321,7 @@ class S6DDRPHY(Module):
 				Instance.Output("SHIFTOUT2"),
 				Instance.Output("SHIFTOUT3"),
 				Instance.Output("SHIFTOUT4"),
-				)
+			)
 
 
 		# 
@@ -329,7 +330,6 @@ class S6DDRPHY(Module):
 		self.comb += drive_dq.eq(d_dfi[phy_settings.wrphase].wrdata_en)
 		sd_sys += d_drive_dq.eq(drive_dq)
 
-
 		d_dfi_wrdata_en = Signal()
 		sd_sys += d_dfi_wrdata_en.eq(d_dfi[phy_settings.wrphase].wrdata_en)
 		

software/bios/sdram.c

@@ -8,7 +8,7 @@
 
 #include "sdram.h"
 
-void cdelay(int i)
+static void cdelay(int i)
 {
 	while(i > 0) {
 		__asm__ volatile("nop");