s6ddrphy: style and other minor fixes
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@ -11,6 +11,7 @@ tools/flterm
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tools/mkmmimg
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tools/byteswap
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software/include/hw/csr.h
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software/include/hw/sdram_phy.h
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software/videomixer/dvisampler0.c
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software/videomixer/dvisampler0.h
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software/videomixer/dvisampler1.c
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@ -67,14 +67,13 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
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return r
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def get_sdram_phy_header(sdram_phy):
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if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("sdram phy header generator only supports SDR, DDR, LPDDR and DDR2")
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raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
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r = "#ifndef __HW_SDRAM_PHY_H\n#define __SDRAM_PHY_H\n"
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r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
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r += "extern void cdelay(int i);\n"
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r += "static void cdelay(int i);\n"
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#
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# commands_px functions
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@ -126,7 +125,7 @@ static void command_p{n}(int cmd)
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return r
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r += "static void init_sequence(void) {\n"
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r += "static void init_sequence(void)\n{\n"
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cl = sdram_phy.phy_settings.cl
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@ -18,7 +18,6 @@
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# Todo:
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# - use CSR for bitslip?
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# - move sdram clk generation to phy?
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from migen.fhdl.std import *
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from migen.bus.dfi import *
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@ -26,7 +25,6 @@ from migen.genlib.record import *
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class S6DDRPHY(Module):
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def __init__(self, pads, phy_settings, bitslip):
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if phy_settings.type not in ["DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
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@ -48,8 +46,6 @@ class S6DDRPHY(Module):
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# sdram_full_rd_clk : full rate sdram write clk
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sd_sys = getattr(self.sync, "sys")
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sd_sdram_half = getattr(self.sync, "sdram_half")
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sd_sdram_full_wr = getattr(self.sync, "sdram_full_wr")
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sd_sdram_full_rd = getattr(self.sync, "sdram_full_rd")
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sys_clk = ClockSignal("sys")
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sdram_half_clk = ClockSignal("sdram_half")
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@ -102,10 +98,10 @@ class S6DDRPHY(Module):
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#
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# Bitslip
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#
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bitslip_cnt = Signal(4)
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bitslip_cnt = Signal(4)
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bitslip_inc = Signal()
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sd_sys +=[
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sd_sys += [
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If(bitslip_cnt==bitslip,
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bitslip_inc.eq(0)
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).Else(
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@ -120,7 +116,10 @@ class S6DDRPHY(Module):
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sdram_half_clk_n = Signal()
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self.comb += sdram_half_clk_n.eq(~sdram_half_clk)
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postamble, drive_dqs, dqs_t_d0, dqs_t_d1 = (Signal() for i in range(4))
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postamble = Signal()
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drive_dqs = Signal()
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dqs_t_d0 = Signal()
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dqs_t_d1 = Signal()
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dqs_o = Signal(d//8)
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dqs_t = Signal(d//8)
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@ -131,7 +130,6 @@ class S6DDRPHY(Module):
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]
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for i in range(d//8):
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# DQS output
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self.specials += Instance("ODDR2",
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Instance.Parameter("DDR_ALIGNMENT", "C1"),
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@ -182,28 +180,32 @@ class S6DDRPHY(Module):
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for i in range(2*nphases)]
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for n, phase in enumerate(self.dfi.phases):
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self.comb +=[
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self.comb += [
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d_dfi[n].wrdata.eq(phase.wrdata),
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d_dfi[n].wrdata_mask.eq(phase.wrdata_mask),
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d_dfi[n].wrdata_en.eq(phase.wrdata_en),
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d_dfi[n].rddata_en.eq(phase.rddata_en),
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]
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sd_sys +=[
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d_dfi[nphases+n].wrdata.eq(phase.wrdata),
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d_dfi[nphases+n].wrdata_mask.eq(phase.wrdata_mask)
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sd_sys += [
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d_dfi[nphases+n].wrdata.eq(phase.wrdata),
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d_dfi[nphases+n].wrdata_mask.eq(phase.wrdata_mask)
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]
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drive_dq, drive_dq_n, d_drive_dq, d_drive_dq_n = (Signal() for i in range(4))
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self.comb +=[
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drive_dq = Signal()
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drive_dq_n = Signal()
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d_drive_dq = Signal()
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d_drive_dq_n = Signal()
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self.comb += [
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drive_dq_n.eq(~drive_dq),
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d_drive_dq_n.eq(~d_drive_dq)
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]
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dq_t, dq_o, dq_i = (Signal(d) for i in range(3))
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dq_t = Signal(d)
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dq_o = Signal(d)
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dq_i = Signal(d)
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for i in range(d):
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# Data serializer
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self.specials += Instance("OSERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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@ -240,7 +242,7 @@ class S6DDRPHY(Module):
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Instance.Output("SHIFTOUT2"),
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Instance.Output("SHIFTOUT3"),
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Instance.Output("SHIFTOUT4"),
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)
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)
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# Data deserializer
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self.specials += Instance("ISERDES2",
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@ -272,7 +274,7 @@ class S6DDRPHY(Module):
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Instance.Output("VALID"),
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Instance.Output("INCDEC"),
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Instance.Output("SHIFTOUT")
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)
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)
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# Data buffer
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self.specials += Instance("IOBUF",
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@ -280,10 +282,9 @@ class S6DDRPHY(Module):
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Instance.Output("O", dq_i[i]),
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Instance.Input("T", dq_t[i]),
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Instance.InOut("IO", pads.dq[i])
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)
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)
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for i in range(d//8):
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# Mask serializer
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self.specials += Instance("OSERDES2",
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Instance.Parameter("DATA_WIDTH", 4),
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@ -320,7 +321,7 @@ class S6DDRPHY(Module):
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Instance.Output("SHIFTOUT2"),
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Instance.Output("SHIFTOUT3"),
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Instance.Output("SHIFTOUT4"),
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)
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)
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#
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@ -329,7 +330,6 @@ class S6DDRPHY(Module):
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self.comb += drive_dq.eq(d_dfi[phy_settings.wrphase].wrdata_en)
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sd_sys += d_drive_dq.eq(drive_dq)
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d_dfi_wrdata_en = Signal()
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sd_sys += d_dfi_wrdata_en.eq(d_dfi[phy_settings.wrphase].wrdata_en)
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@ -8,7 +8,7 @@
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#include "sdram.h"
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void cdelay(int i)
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static void cdelay(int i)
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{
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while(i > 0) {
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__asm__ volatile("nop");
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