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sim/verilator: Revert regular_comb change and just pass it to get_verilog as before.

This commit is contained in:
Florent Kermarrec 2021-11-05 16:27:38 +01:00
parent 67431f4109
commit 2740dd34e7
1 changed files with 4 additions and 4 deletions
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8
litex/build/sim/verilator.py
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@ -204,11 +204,11 @@ class SimVerilatorToolchain:
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
if regular_comb:
raise ValueError("SimVerilatorToolchain disallows regular_comb=True")
# Generate verilog # Generate verilog
v_output = platform.get_verilog(fragment, name=build_name) v_output = platform.get_verilog(fragment,
name = build_name,
regular_comb = regular_comb
)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)