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Add tracelength report generation by default to help with board layout

This commit is contained in:
bunnie 2017-12-27 22:40:39 +08:00
parent b463b2169b
commit 282f22f09e
1 changed files with 1 additions and 0 deletions
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litex/build/xilinx/vivado.py
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@ -119,6 +119,7 @@ class XilinxVivadoToolchain:
tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name)) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name))
tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name)) tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name))
tcl.append("report_io -file {}_io.rpt".format(build_name)) tcl.append("report_io -file {}_io.rpt".format(build_name))
tcl.append("write_csv -force {}_tracelength.csv".format(build_name))
tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name)) tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name)) tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
tcl.append("route_design") tcl.append("route_design")