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soc/integration/soc_core: make nmi interrupt optional

This commit is contained in:
Florent Kermarrec 2017-12-03 23:06:22 +01:00
parent c1eba9a6cc
commit 284b16e2c1
1 changed files with 4 additions and 1 deletions
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5
litex/soc/integration/soc_core.py
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@ -50,7 +50,6 @@ class SoCCore(Module):
} }
interrupt_map = {} interrupt_map = {}
soc_interrupt_map = { soc_interrupt_map = {
"nmi": 0, # Reserve zero for "non-maskable interrupt"
"timer0": 1, # LiteX Timer "timer0": 1, # LiteX Timer
"uart": 2, # LiteX UART (IRQ 2 for UART matches mor1k standard config). "uart": 2, # LiteX UART (IRQ 2 for UART matches mor1k standard config).
} }
@ -69,6 +68,7 @@ class SoCCore(Module):
csr_data_width=8, csr_address_width=14, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200, uart_stub=False, with_uart=True, uart_baudrate=115200, uart_stub=False,
ident="", ident_version=False, ident="", ident_version=False,
reserve_nmi_interrupt=True,
with_timer=True): with_timer=True):
self.config = dict() self.config = dict()
@ -132,6 +132,9 @@ class SoCCore(Module):
self.add_constant("CSR_DATA_WIDTH", csr_data_width) self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
if reserve_nmi_interrupt:
self.soc_interrupt_map["nmi"] = 0 # Reserve zero for "non-maskable interrupt"
if with_uart: if with_uart:
if uart_stub: if uart_stub:
self.submodules.uart = uart.UARTStub() self.submodules.uart = uart.UARTStub()