Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fhdl/memory/write: Avoid slicing data when memory.width == port.we_granularity.

This commit is contained in:
Florent Kermarrec 2021-10-30 22:42:55 +02:00
parent 942e50b992
commit 28c8436e01
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/gen/fhdl/memory.py
View File

@ -110,7 +110,8 @@ def memory_emit_verilog(memory, ns, add_data_file):
r += f"\tif ({gn(port.we)}{wbit})\n" r += f"\tif ({gn(port.we)}{wbit})\n"
lbit = i*port.we_granularity lbit = i*port.we_granularity
hbit = (i+1)*port.we_granularity-1 hbit = (i+1)*port.we_granularity-1
r += f"\t\t{gn(memory)}[{gn(port.adr)}][{hbit}:{lbit}] <= {gn(port.dat_w)}[{hbit}:{lbit}];\n" dslc = f"[{hbit}:{lbit}]" if (memory.width != port.we_granularity) else ""
r += f"\t\t{gn(memory)}[{gn(port.adr)}]{dslc} <= {gn(port.dat_w)}{dslc};\n"
# Read Logic. # Read Logic.
if not port.async_read: if not port.async_read: