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efinix/ifacewriter: Renamer br0_pll to dram_pll.

This commit is contained in:
Florent Kermarrec 2021-11-12 19:44:20 +01:00
parent 0a90a0eee9
commit 291402608e
1 changed files with 8 additions and 8 deletions
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16
litex/build/efinix/ifacewriter.py
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@ -212,14 +212,14 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
def generate_pll_dram(self):
return """
design.create_block("br0_pll", block_type="PLL")
design.set_property("br0_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
design.gen_pll_ref_clock("br0_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="br0_pll_clkin", ext_refclk_no="0")
design.set_property("br0_pll","LOCKED_PIN","br0_pll_locked", block_type="PLL")
design.set_property("br0_pll","RSTN_PIN","br0_pll_rstn", block_type="PLL")
design.set_property("br0_pll", {"CLKOUT0_PIN" : "br0_pll_CLKOUT0"}, block_type="PLL")
design.set_property("br0_pll","CLKOUT0_PHASE","0","PLL")
calc_result = design.auto_calc_pll_clock("br0_pll", {"CLKOUT0_FREQ": "400.0"})
design.create_block("dram_pll", block_type="PLL")
design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0")
design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL")
design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL")
design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL")
design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL")
calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
"""
def generate(self, partnumber):